LuminaSensum/arm-trusted-firmware

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LuminaSensum / arm-trusted-firmware

2020-06-23	ccf5863 Browse files » Merge changes Ifc34f2e9,Iefd58159 into integration ... * changes: Workaround for Cortex A76 erratum 1800710 Workaround for Cortex A76 erratum 1791580 Lauren Wehrmeister authored on 23 Jun 2020 TrustedFirmware Code Review committed on 23 Jun 2020
	5703c73 Browse files » Fix usage of incorrect function name ... Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com> Change-Id: Ic387630c096361ea9a963cde0018a0efb63e3bd2 Sheetal Tigadoli committed on 23 Jun 2020
	993dc0e Browse files » Merge "FFA Version interface update" into integration Manish Pandey authored on 23 Jun 2020 TrustedFirmware Code Review committed on 23 Jun 2020
	ebd34be Browse files » doc: Add a binding document for COT descriptors ... Added a binding document for COT descriptors which is going to be used in order to create COT desciptors at run-time. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: Ic54519b0e16d145cd1609274a00b137a9194e8dd Manish V Badarkhe committed on 23 Jun 2020
	4388f28 Browse files » FFA Version interface update ... Change handler of FFA version interface: - Return SPMD's version if the origin of the call is secure; - Return SPMC's version if origin is non-secure. Signed-off-by: J-Alves <joao.alves@arm.com> Change-Id: I0d1554da79b72b1e02da6cc363a2288119c32f44 J-Alves committed on 23 Jun 2020
	450e15a Browse files » stm32mp1: SP_MIN embeds Arm Architecture services ... Embed Arch Architecture SMCCC services in stm32mp1 SP_MIN. This service is needed by Linux kernel to setup the SMCCC conduit used by its SCMI SMC transport driver. Change-Id: I454a7ef3048a77ab73fff945e8115b60445d5841 Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Etienne Carriere committed on 23 Jun 2020
	0754143 Browse files » stm32mp1: use last page of SYSRAM as SCMI shared memory ... SCMI shared memory is used to exchange message payloads between secure SCMI services and non-secure SCMI agents. It is mapped uncached (device) mainly to conform to existing support in the Linux kernel. Note that executive messages are mostly short (few 32bit words) hence not using cache will not penalize much performances. Platform stm32mp1 shall configure ETZPC to harden properly the secure and non-secure areas of the SYSRAM address space, that before CPU accesses the shared memory when mapped non-secure. This change defines STM32MP_SEC_SYSRAM_BASE/STM32MP_SEC_SYSRAM_SIZE and STM32MP_NS_SYSRAM_BASE/STM32MP_NS_SYSRAM_SIZE. Change-Id: I71ff02a359b9668ae1c5a71b5f102cf3d310f289 Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Etienne Carriere committed on 23 Jun 2020
2020-06-22	dcbfbcb Browse files » Workaround for Cortex A76 erratum 1800710 ... Cortex A76 erratum 1800710 is a Cat B erratum, present in older revisions of the Cortex A76 processor core. The workaround is to set a bit in the ECTLR_EL1 system register, which disables allocation of splintered pages in the L2 TLB. This errata is explained in this SDEN: https://static.docs.arm.com/sden885749/g/Arm_Cortex_A76_MP052_Software_Developer_Errata_Notice_v20.pdf Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Ifc34f2e9e053dcee6a108cfb7df7ff7f497c9493 johpow01 committed on 22 Jun 2020
	d7b08e6 Browse files » Workaround for Cortex A76 erratum 1791580 ... Cortex A76 erratum 1791580 is a Cat B erratum present in earlier revisions of the Cortex A76. The workaround is to set a bit in the implementation defined CPUACTLR2 register, which forces atomic store operations to write-back memory to be performed in the L1 data cache. This errata is explained in this SDEN: https://static.docs.arm.com/sden885749/g/Arm_Cortex_A76_MP052_Software_Developer_Errata_Notice_v20.pdf Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Iefd58159b3f2e2286138993317b98e57dc361925 johpow01 committed on 22 Jun 2020
	3fbec43 Browse files » Merge changes from topic "tegra-memctrlv2-vpr-resize-bugfix" into integration ... * changes: Tegra: sanity check NS address and size before use Tegra: memctrl_v2: fixup sequence to resize video memory Manish Pandey authored on 22 Jun 2020 TrustedFirmware Code Review committed on 22 Jun 2020
	b667b36 Browse files » Merge "TF-A GIC driver: Add barrier before eoi" into integration Madhukar Pappireddy authored on 22 Jun 2020 TrustedFirmware Code Review committed on 22 Jun 2020
	34dae47 Browse files » Merge "TF-A: Add ARMv8.5 'bti' build option" into integration Mark Dykes authored on 22 Jun 2020 TrustedFirmware Code Review committed on 22 Jun 2020
	453e12c Browse files » Merge changes from topic "scmi-msg" into integration ... * changes: drivers/scmi-msg: smt entry points for incoming messages drivers/scmi-msg: support for reset domain protocol drivers/scmi-msg: support for clock protocol drivers/scmi-msg: driver for processing scmi messages Manish Pandey authored on 22 Jun 2020 TrustedFirmware Code Review committed on 22 Jun 2020
	66f05b2 Browse files » Merge "Fix typo in file Header guard" into integration Sandrine Bailleux authored on 22 Jun 2020 TrustedFirmware Code Review committed on 22 Jun 2020
	5eb16c4 Browse files » TF-A GIC driver: Add barrier before eoi ... It is desired to have the peripheral writes completed to clear the interrupt condition and de-assert the interrupt request to GIC before EOI write. Failing which spurious interrupt will occurred. A barrier is needed to ensure peripheral register write transfers are complete before EOI is done. GICv2 memory mapped DEVICE nGnR(n)E writes are ordered from core point of view. However these writes may pass over different interconnects, bridges, buffers leaving some rare chances for the actual write to complete out of order. GICv3 ICC EOI system register writes have no ordering against nGnR(n)E memory writes as they are over different interfaces. Hence a dsb can ensure from core no writes are issued before the previous writes are complete. Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com> Change-Id: Ie6362009e2f91955be99dca8ece14ade7b4811d6 Sandeep Tripathy committed on 22 Jun 2020
	71c074c Browse files » Merge "Tegra: introduce support for GICv3" into integration Olivier Deprez authored on 22 Jun 2020 TrustedFirmware Code Review committed on 22 Jun 2020
	49fe535 Browse files » Fix typo in file Header guard ... Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com> Change-Id: Iaf6deaeee2069720518221157edbb052bc42850a Sheetal Tigadoli committed on 22 Jun 2020
2020-06-21	685e560 Browse files » Tegra: sanity check NS address and size before use ... This patch updates the 'bl31_check_ns_address()' helper function to check that the memory address and size passed by the NS world are not zero. The helper fucntion also returns the error code as soon as it detects inconsistencies, to avoid multiple error paths from kicking in for the same input parameters. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I46264f913954614bedcbde12e47ea0c70cd19be0 Varun Wadekar committed on 21 Jun 2020
2020-06-19	47d1773 Browse files » plat: marvell: armada: a8k: add OP-TEE OS MMU tables ... Adjust the latest OP-TEE memory definitions to the newest TF-A baseline. Change-Id: Ib9c82b85f868adaf3c7285eb340486bda9c59c36 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Konstantin Porotchkin authored on 15 Apr 2019 Marcin Wojtas committed on 19 Jun 2020
	5a40d70 Browse files » drivers: marvell: add support for mapping the entire LLC to SRAM ... Add llc_sram_enable() and llc_sram_disable() APIs to Marvell cache_lls driver. Add LLC_SRAM definition to Marvell common makefile - disabled by the default. Add description of LLC_SRAM flag to the build documentation. Change-Id: Ib348e09752ce1206d29268ef96c9018b781db182 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Konstantin Porotchkin authored on 31 Mar 2019 Marcin Wojtas committed on 19 Jun 2020
	8544080 Browse files » plat: marvell: armada: add LLC SRAM CCU setup for AP806/AP807 platforms ... Extend the CCU tables with secure SRAM window in all board setups that uses SoCs based on AP806/AP807 North Bridges Change-Id: I4dc315e4ea847562ac8648d8a8739244b548c70e Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Konstantin Porotchkin authored on 31 Mar 2019 Marcin Wojtas committed on 19 Jun 2020
	94d6f48 Browse files » plat: marvell: armada: reduce memory size reserved for FIP image ... It is not needed to reserve 64MB for FIP. Limit this to 4MB for both supported Armada SoC families. Change-Id: I58a8ce4408a646fe1afd3c1ea1ed54007c8d205d Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> [Extract from bigger commit] Signed-off-by: Marcin Wojtas <mw@semihalf.com> Marcin Wojtas committed on 19 Jun 2020
	63a0b12 Browse files » plat: marvell: armada: platform definitions cleanup ... - Remove TRUSTED_DRAM_BASE TRUSTED_DRAM_SIZE MARVELL_TRUSTED_SRAM_BASE - Rename PLAT_MARVELL_TRUSTED_DRAM_* -> PLAT_MARVELL_TRUSTED_RAM_* PLAT_MARVELL_TRUSTED_SRAM_* -> MARVELL_TRUSTED_DRAM_* MARVELL_MAP_SHARED_RAM -> MARVELL_MAP_SECURE_RAM - Move MARVELL_TRUSTED_DRAM_SIZE to marvell_def.h - Enable MARVELL_MAP_SECURE_RAM region in BL2U memory map - Add dependency of MARVELL_MAP_SHARED_RAM on LLC_SRAM - Add minor style improvents Change-Id: Iebc03361e4f88489af1597f54e137b27c241814c Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> [Improve patch after rebase] Signed-off-by: Marcin Wojtas <mw@semihalf.com> Konstantin Porotchkin authored on 19 Jun 2020 Marcin Wojtas committed on 19 Jun 2020
	c96aa7f Browse files » plat: marvell: armada: a8k: check CCU window state before loading MSS BL2 ... Make sure the current CCU window is not in use before adding a new address map during MSS BL2 image load preparations. At BL2 stage the CCU Win-2 points to DRAM. If additional mapping is added to MSS BL2 stage initialization, the DDR entry will be destroyed and lead to the system hang. Change-Id: I215e83508acc37d54dab6954d791b9a74cc883ca Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Konstantin Porotchkin authored on 31 Mar 2019 Marcin Wojtas committed on 19 Jun 2020
	957a5ad Browse files » drivers: marvell: add CCU driver API for window state checking ... Add ccu_is_win_enabled() API for checking the CCU window state using AP and window indexes. Change-Id: Ib955a2cac28b2729b0a763f3bbbea28b476a2fe4 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Konstantin Porotchkin authored on 31 Mar 2019 Marcin Wojtas committed on 19 Jun 2020
	772aa5b Browse files » drivers: marvell: align and extend llc macros ... Make all LLC-related macros to start with the same prefix Add more LLC control registers definitions This patch is a preparation step for LLC SRAM support Change-Id: I0a4f0fc83e8ef35be93dd239a85f2a9f88d1ab19 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Konstantin Porotchkin authored on 25 Mar 2019 Marcin Wojtas committed on 19 Jun 2020
	e825176 Browse files » plat: marvell: a8k: move address config of cp1/2 to BL2 ... The configuration space of each standalone CP was updated in BL31. Loading FW procedure take places earlier in SCP_BL2. It needs to be done after access to each CP is provided. Moving the proper configuration from BL31 to BL2 solves it. Change-Id: I44cf88dfd4ebf09130544332bfdd3d16ef2674ea Signed-off-by: Ben Peled <bpeled@marvell.com> Ben Peled authored on 26 Mar 2019 Marcin Wojtas committed on 19 Jun 2020
	cdfbbfe Browse files » plat: marvell: armada: re-enable BL32_BASE definition ... As a preparation to support proper loading the OPTEE OS image, enable the BL32 specific defines in case the SPD is used. On the occasion move two BL32-related macros to marvell_def.h and fix BL32_LIMIT definition. Change-Id: Id4e2d81833bc1895650cca8b0fc0bfc341cf77f3 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Marcin Wojtas <mw@semihalf.com> Konstantin Porotchkin authored on 14 Mar 2019 Marcin Wojtas committed on 19 Jun 2020
	814ce2f Browse files » plat: marvell: a8k: extend includes to take advantage of the phy_porting_layer ... The phy porting layer uses defaults defined in "phy-default-porting-layer.h" when board specific file "phy-porting-layer.h" is not found. Because of the regression the board specific directory was not included, therefore all boards used default parameters. Change-Id: I66e5e6eb8a39cca5aeeb4de6dab2ceddc39c1e31 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Grzegorz Jaszczyk authored on 28 Mar 2019 Marcin Wojtas committed on 19 Jun 2020
	050eb19 Browse files » marvell: comphy: initialize common phy selector for AP mode ... Configuring common phy selector which was missing for AP mode. Change-Id: I15be1ba50b8aafe9094734abec139d72c18bb224 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Grzegorz Jaszczyk authored on 28 Mar 2019 Marcin Wojtas committed on 19 Jun 2020