LuminaSensum/arm-trusted-firmware

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LuminaSensum / arm-trusted-firmware

2020-03-10	6e19bd5 Browse files » TF-A GICv3 driver: Separate GICD and GICR accessor functions ... This patch provides separation of GICD, GICR accessor functions and adds new macros for GICv3 registers access as a preparation for GICv3.1 and GICv4 support. NOTE: Platforms need to modify to include both 'gicdv3_helpers.c' and 'gicrv3_helpers.c' instead of the single helper file previously. Change-Id: I1641bd6d217d6eb7d1228be3c4177b2d556da60a Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com> Alexei Fedorov committed on 10 Mar 2020
2020-03-10	65012c0 Browse files » Merge changes from topic "tegra-downstream-02182020" into integration ... * changes: Tegra186: store TZDRAM base/size to scratch registers Tegra186: add SE support to generate SHA256 of TZRAM Tegra186: add support for bpmp_ipc driver Tegra210: disable ERRATA_A57_829520 Tegra194: memctrl: add support for MIU4 and MIU5 Tegra194: memctrl: remove support to reconfigure MSS Tegra: fiq_glue: remove bakery locks from interrupt handler Tegra210: SE: add context save support Tegra210: update the PMC blacklisted registers Tegra: disable CPUACTLR access from lower exception levels cpus: denver: fixup register used to store return address Olivier Deprez authored on 10 Mar 2020 TrustedFirmware Code Review committed on 10 Mar 2020
2020-03-09	7d74487 Browse files » Tegra186: store TZDRAM base/size to scratch registers ... This patch saves the TZDRAM base and size values to secure scratch registers, for the WB0. The WB0 reads these values and uses them to verify integrity of the TZDRAM aperture. Change-Id: Ic70914cb958249f06cb58025a24d13734a85e16e Signed-off-by: Jeetesh Burman <jburman@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Varun Wadekar committed on 9 Mar 2020
	4eed9c8 Browse files » Tegra186: add SE support to generate SHA256 of TZRAM ... The BL3-1 firmware code is stored in TZSRAM on Tegra186 platforms. This memory loses power when we enter System Suspend and so its contents are stored to TZDRAM, before entry. This opens up an attack vector where the TZDRAM contents might be tampered with when we are in the System Suspend mode. To mitigate this attack the SE engine calculates the hash of entire TZSRAM and stores it in PMC scratch, before we copy data to TZDRAM. The WB0 code will validate the TZDRAM and match the hash with the one in PMC scratch. This patch adds driver for the SE engine, with APIs to calculate the hash and store SE SHA256 hash-result to PMC scratch registers. Change-Id: Ib487d5629225d3d99bd35d44f0402d6d3cf27ddf Signed-off-by: Jeetesh Burman <jburman@nvidia.com> Jeetesh Burman authored on 19 Jul 2018 Varun Wadekar committed on 9 Mar 2020
	3827aa8 Browse files » Tegra186: add support for bpmp_ipc driver ... This patch enables the bpmp-ipc driver for Tegra186 platforms, to ask BPMP firmware to toggle SE clock. Change-Id: Ie63587346c4d9b7e54767dbee17d0139fa2818ae Signed-off-by: Jeetesh Burman <jburman@nvidia.com> Jeetesh Burman authored on 31 May 2018 Varun Wadekar committed on 9 Mar 2020
	be85f0f Browse files » Tegra210: disable ERRATA_A57_829520 ... ERRATA_A57_829520 disables "indirect branch prediction" for EL1 on cpu reset, leading to 15% drop in CPU performance with coremark benchmarks. Tegra210 already has a hardware fix for ARM BUG#829520,so this errata is not needed. This patch disables the errata to get increased performance numbers. Change-Id: I0b42e8badd19a8101f6a55d80eb2d953597d3c20 Signed-off-by: Mithun Maragiri <mmaragiri@nvidia.com> Mithun Maragiri authored on 20 Jul 2018 Varun Wadekar committed on 9 Mar 2020
	a69a30f Browse files » Tegra194: memctrl: add support for MIU4 and MIU5 ... This patch adds support for memqual miu 4,5. The MEMQUAL engine has miu0 to miu7 in which miu6 and miu7 is hardwired to bypass SMMU. So only miu0 to miu5 support is provided. Change-Id: Ib350334eec521e65f395f1c3205e2cdaf464ebea Signed-off-by: Pravin <pt@nvidia.com> Pravin authored on 11 May 2018 Varun Wadekar committed on 9 Mar 2020
	4b74f6d Browse files » Tegra194: memctrl: remove support to reconfigure MSS ... As bpmp-fw is running at the same time as ATF, and the mss client reconfiguration sequence involves performing a hot flush resets on bpmp, there is a chance that bpmp-fw is trying to perform accesses while the hot flush is active. Therefore, the mss client reconfigure has been moved to System Suspend resume fw and bootloader, and it can be removed from here. Change-Id: I34019ad12abea9681f5e180af6bc86f2c4c6fc74 Signed-off-by: Stefan Kristiansson <stefank@nvidia.com> Stefan Kristiansson authored on 24 Apr 2018 Varun Wadekar committed on 9 Mar 2020
	f617868 Browse files » Tegra: fiq_glue: remove bakery locks from interrupt handler ... This patch removes usage of bakery_locks from the FIQ handler, as it creates unnecessary dependency whenever the watchdog timer interrupt fires. All operations inside the interrupt handler are 'reads', so no need for serialization. Change-Id: I3f675e610e4dabc5b1435fdd24bc28e424f5a8e4 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Varun Wadekar committed on 9 Mar 2020
	41554fb Browse files » Tegra210: SE: add context save support ... Tegra210B01 SoCs support atomic context save for the two SE hardware engines. Tegra210 SoCs have support for only one SE engine and support a software based save/restore mechanism instead. This patch updates the SE driver to make this change. Change-Id: Ia5e5ed75d0fe011f17809684bbc2ed2338925946 Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com> Harvey Hsieh authored on 10 Apr 2018 Varun Wadekar committed on 9 Mar 2020
	24902fa Browse files » Tegra210: update the PMC blacklisted registers ... Update the list to include PMC registers that the NS world cannot access even with smc calls. Change-Id: I588179b56ebc0c29200b55e6d61535fd3a7a3b7e Signed-off-by: kalyani chidambaram <kalyanic@nvidia.com> kalyani chidambaram authored on 19 Jun 2018 Varun Wadekar committed on 9 Mar 2020
	b1481cf Browse files » Tegra: disable CPUACTLR access from lower exception levels ... This patch resets the macros to update the CPUACTLR_ELx to make them generic for all exception levels. Change-Id: I33e9b860efb543934b654a2f5d775135df7f1aa6 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Varun Wadekar committed on 9 Mar 2020
	e6c0da1 Browse files » cpus: denver: fixup register used to store return address ... The denver_enable_dco and denver_disable_dco use register X3 to store the return address. But X3 gets over-written by other functions, downstream. This patch stores the return address to X18 instead, to fix this anomaly. Change-Id: Ic40bfc1d9abaa7b90348843b9ecd09521bb4ee7b Signed-off-by: Kalyani Chidambaram <kalyanic@nvidia.com> Kalyani Chidambaram authored on 8 Oct 2018 Varun Wadekar committed on 9 Mar 2020
	efe30cb Browse files » Merge "aarch32: stop speculative execution past exception returns" into integration Mark Dykes authored on 9 Mar 2020 TrustedFirmware Code Review committed on 9 Mar 2020
	091576e Browse files » Merge changes from topic "tbbr/fw_enc" into integration ... * changes: docs: qemu: Add instructions to boot using FIP image docs: Update docs with firmware encryption feature qemu: Support optional encryption of BL31 and BL32 images qemu: Update flash address map to keep FIP in secure FLASH0 Makefile: Add support to optionally encrypt BL31 and BL32 tools: Add firmware authenticated encryption tool TBB: Add an IO abstraction layer to load encrypted firmwares drivers: crypto: Add authenticated decryption framework Sandrine Bailleux authored on 9 Mar 2020 TrustedFirmware Code Review committed on 9 Mar 2020
	4ebbea9 Browse files » docs: qemu: Add instructions to boot using FIP image ... Update qemu documentation with instructions to boot using FIP image. Also, add option to build TF-A with TBBR and firmware encryption enabled. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Change-Id: Ib3af485d413cd595352034c82c2268d7f4cb120a Sumit Garg committed on 9 Mar 2020
	f97062a Browse files » docs: Update docs with firmware encryption feature ... Update documentation with optional firmware encryption feature. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Change-Id: I26691b18e1ee52a73090954260f26f2865c4e05a Sumit Garg committed on 9 Mar 2020
	a3d0fa3 Browse files » Merge "fdts: a5ds: add ethernet node in devicetree" into integration Manish Pandey authored on 9 Mar 2020 TrustedFirmware Code Review committed on 9 Mar 2020
	a1463c8 Browse files » Merge "uniphier: shrink UNIPHIER_ROM_REGION_SIZE" into integration Sandrine Bailleux authored on 9 Mar 2020 TrustedFirmware Code Review committed on 9 Mar 2020
	366d95f Browse files » Merge "TSP: corrected log information" into integration Sandrine Bailleux authored on 9 Mar 2020 TrustedFirmware Code Review committed on 9 Mar 2020
2020-03-06	a16bc84 Browse files » TSP: corrected log information ... In CPU resume function, CPU suspend count was printed instead of CPU resume count. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I0c081dc03a4ccfb2129687f690667c5ceed00a5f Manish Pandey committed on 6 Mar 2020
	548654b Browse files » uniphier: shrink UNIPHIER_ROM_REGION_SIZE ... Currently, the ROM region is needlessly too large. The on-chip SRAM region of the next SoC will start from 0x04000000, and this will cause the region overlap. Mapping 0x04000000 for the ROM is enough. Change-Id: I85ce0bb1120ebff2e3bc7fd13dc0fd15dfff5ff6 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Masahiro Yamada committed on 6 Mar 2020
	03ea84c Browse files » Merge "driver/arm/css: minor bug fix" into integration Alexei Fedorov authored on 6 Mar 2020 TrustedFirmware Code Review committed on 6 Mar 2020
	5185776 Browse files » qemu: Support optional encryption of BL31 and BL32 images ... Enable encryption IO layer to be stacked above FIP IO layer for optional encryption of Bl31 and BL32 images in case ENCRYPT_BL31 or ENCRYPT_BL32 build flag is set. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Change-Id: I24cba64728861e833abffc3d5d9807599c49feb6 Sumit Garg committed on 6 Mar 2020
	a886bbe Browse files » qemu: Update flash address map to keep FIP in secure FLASH0 ... Secure FLASH0 memory map looks like: - Offset: 0 to 256K -> bl1.bin - Offset: 256K to 4.25M -> fip.bin FLASH1 is normally used via UEFI/edk2 to keep varstore. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Change-Id: I6883f556c22d6a5d3fa3846c703bebc2abe36765 Sumit Garg committed on 6 Mar 2020
	c6ba9b4 Browse files » Makefile: Add support to optionally encrypt BL31 and BL32 ... Following build flags have been added to support optional firmware encryption: - FW_ENC_STATUS: Top level firmware's encryption numeric flag, values: 0: Encryption is done with Secret Symmetric Key (SSK) which is common for a class of devices. 1: Encryption is done with Binding Secret Symmetric Key (BSSK) which is unique per device. - ENC_KEY: A 32-byte (256-bit) symmetric key in hex string format. It could be SSK or BSSK depending on FW_ENC_STATUS flag. - ENC_NONCE: A 12-byte (96-bit) encryption nonce or Initialization Vector (IV) in hex string format. - ENCRYPT_BL31: Binary flag to enable encryption of BL31 firmware. - ENCRYPT_BL32: Binary flag to enable encryption of Secure BL32 payload. Similar flags can be added to encrypt other firmwares as well depending on use-cases. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Change-Id: I94374d6830ad5908df557f63823e58383d8ad670 Sumit Garg committed on 6 Mar 2020
	90aa901 Browse files » tools: Add firmware authenticated encryption tool ... Add firmware authenticated encryption tool which utilizes OpenSSL library to encrypt firmwares using a key provided via cmdline. Currently this tool supports AES-GCM as an authenticated encryption algorithm. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Change-Id: I60e296af1b98f1912a19d5f91066be7ea85836e4 Sumit Garg committed on 6 Mar 2020
	2be57b8 Browse files » TBB: Add an IO abstraction layer to load encrypted firmwares ... TBBR spec advocates for optional encryption of firmwares (see optional requirement: R060_TBBR_FUNCTION). So add an IO abstaction layer to support firmware decryption that can be stacked above any underlying IO/ packaging layer like FIP etc. It aims to provide a framework to load any encrypted IO payload. Also, add plat_get_enc_key_info() to be implemented in a platform specific manner as handling of encryption key may vary from one platform to another. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Change-Id: I9892e0ddf00ebecb8981301dbfa41ea23e078b03 Sumit Garg committed on 6 Mar 2020
	7cda17b Browse files » drivers: crypto: Add authenticated decryption framework ... Add framework for autheticated decryption of data. Currently this patch optionally imports mbedtls library as a backend if build option "DECRYPTION_SUPPORT = aes_gcm" is set to perform authenticated decryption using AES-GCM algorithm. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Change-Id: I2966f0e79033151012bf4ffc66f484cd949e7271 Sumit Garg committed on 6 Mar 2020
	d95f7a7 Browse files » Merge changes from topic "spmd-sel2" into integration ... * changes: SPMD: add command line parameter to run SPM at S-EL2 or S-EL1 SPMD: smc handler qualify secure origin using booleans SPMD: SPMC init, SMC handler cosmetic changes SPMD: [tegra] rename el1_sys_regs structure to sys_regs SPMD: Adds partially supported EL2 registers. SPMD: save/restore EL2 system registers. Olivier Deprez authored on 6 Mar 2020 TrustedFirmware Code Review committed on 6 Mar 2020