plat: intel: Add BL2 support for Stratix 10 SoC ...

This adds BL2 support for Intel Stratix 10 SoC FPGA.
Functionality includes:
- Release and setup peripherals from reset
- Calibrate DDR
- ECC DDR Scrubbing
- Load FIP (bl31 and bl33)

Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>

Merge pull request #1762 from antonio-nino-diaz-arm/an/fix-readme ...

readme: Update list of supported platforms

readme: Update list of supported platforms ...

Change-Id: I13b7b16a13f51bcb83098d7c55701f9ee03859a8
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Merge pull request #1760 from igoropaniuk/rpi3_preloaded_dtb_fix ...

rpi3: fix RPI3_PRELOADED_DTB_BASE usage

Merge pull request #1754 from Anson-Huang/master ...

Add i.MX8 SoC SRTC/cpu-freq SIP runtime service support

Merge pull request #1733 from vwadekar/tf2.0-tegra-downstream-rebase-1.3.19 ...

Tegra downstream rebase 1.3.19

imx: add cpu-freq SIP runtime service support ...

On i.MX8QM/i.MX8QX with system controller inside, the CPU's clock
rate is managed by SCFW(system controller firmware) and can ONLY be
changed from secure world, so SIP runtime service is needed for
setting CPU's clock rate, this patch adds cpu-freq SIP runtime service
support.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

imx: add imx8qm/imx8qx SRTC SIP runtime service support ...

On i.MX8QM/i.MX8QX with system controller inside, the SRTC is
managed by SCFW(system controller firmware) and some functions
like setting SRTC's time etc. can ONLY be requested from secure
world, so SIP runtime service is needed for such kind of operations,
this patch adds SRTC SIP runtime service support for i.MX8QM and
i.MX8QX.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

Support for NXP's i.MX8 SoCs timer IPC ...

NXP's i.MX8 SoCs have system controller (M4 core) which takes
control of timer management, including watchdog, srtc and system
counter etc., other clusters like Cortex-A35 can send out command
via MU (Message Unit) to system controller for timer operation.

This patch adds timer IPC(inter-processor communication) support.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

rpi3: fix RPI3_PRELOADED_DTB_BASE usage ...

In case if `RPI3_PRELOADED_DTB_BASE` isn't defined explicitly with
proper pre-loaded DTB address, `add_define` macro defined in
`make_helpers/build_macros.mk` still supplies this definition to the
compiler like `-DRPI3_PRELOADED_DTB_BASE`, and it's obviously is set to
default value 1.

This simply leads to the wrong `MAP_NS_DTB` region definition (base_va
is set `0x1` instead of `0x00010000`) in `plat/rpi3/rpi3_common.c`:

Which causes aligment check to fail in `mmap_add_region_check()`:
VERBOSE: base_pa: 0x00000001, base_va: 0x00000001, size: 0x00010000
...
ERROR:   mmap_add_region_check() failed. error -22

Signed-off-by: Igor Opaniuk <igor.opaniuk@linaro.org>

Tegra186: mce: remove unused type conversions ...

This patch removes unused type conversions as all the relevant macros
now use U()/ULL(), making these explicit typecasts unnecessary.

Change-Id: I01fb534649db2aaf186406b1aef6897662b44fe3
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

Tegra210: Enable ECC reporting for B01 SKUs ...

This patch enables L2 error correction and parity protection
for Tegra210 on boot and exit from suspend. The previous bootloader
sets the boot parameter, indicating ECC reporting, only for B01 SKUs.

Change-Id: I6927884d375a64c69e2f1e9aed85f95c5e3cb17c
Signed-off-by: Sam Payne <spayne@nvidia.com>

Tegra210: skip the BTB invalidate workaround for B01 SKUs ...

This patch skips the BTB invalidate workaround for Tegra210-B01 chips, as
they have already been fixed in the hardware. To allow the .S file to
include macros, add proper guards to tegra_platform.h.

Change-Id: I0826d3c54faeffc9cb0709331f47cbdf25d4b653
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>

Tegra186: memctrl_v2: Set MC clients ordering as per client needs ...

Set MC Clients ordering as per the clients needs(ordered, BW, ISO/non-ISO)
based on the latest info received from HW team as a part of BW issues debug.

SMMU Client config register are obsolete from T186. Clean up the unnecessary
register definitions and programming of these registers.
Cleanup unnecessary macros as well.

Change-Id: I0d28ae8842a33ed534f6a15bfca3c9926b3d46b2
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>

Tegra210: memmap all the IRAM memory banks ...

This patch memmaps all the IRAM memory banks during boot. The BPMP
firmware might place the channels in any of the IRAMs, so it is better
to map all the banks to avoid surprises.

Change-Id: Ia009a65d227ee50fbb23e511ce509daf41b877ee
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra: bpmp: fix check to see if Atomics block is powered on ...

This patch fixes the logic to check if Atomics hardware block is powered
on during boot

Reported by: Peter De Schrijver <pdeschrijver@nvidia.com>

Change-Id: I4a6521bcee37225d1402321151c48fa631776b8a
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra210: increase MAX_XLAT_TABLES and MAX_MMAP_REGIONS ...

This patch updates the macros to include the newly added IRAM
memory apertures.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I931daa310d738e8bf966f14e11d0631920e9bdde

Tegra186: setup: fix defects flagged by MISRA scan ...

Main fixes:

Added explicit casts (e.g. 0U) to integers in order for them to be
compatible with whatever operation they're used in [Rule 10.1]

Force operands of an operator to the same type category [Rule 10.4]

Added curly braces ({}) around if statements in order to
make them compound [Rule 15.6]

Change-Id: I4840c3122939f736113d61f1462af3bd7b0b5085
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

Tegra186: PM: fix MISRA defects in plat_psci_handlers.c ...

Main fixes:

Added explicit casts (e.g. 0U) to integers in order for them to be
compatible with whatever operation they're used in [Rule 10.1]

convert object type to match the type of function parameters
[Rule 10.3]

Force operands of an operator to the same type category [Rule 10.4]

Fix implicit widening of composite assignment [Rule 10.6]

Change-Id: I5840a07f37beefc3326ac56d0b4a4701602bd8a8
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

Tegra186: mce: remove unwanted print messages ...

This patch removes unwanted error prints from the MCE command
handler, to reduce the code complexity for this function.

Tested with 'pmccabe'

Change-Id: I375d289db1df9e119eeb1830210974457c8905a4
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra186: remove support for Quasi System power off (SC8) state ...

This patch removes support for the SC8 power state as the feature is no
longer required for Tegra186 projects.

Change-Id: I622a5ddcffe025b9b798801d09bbb856853befd7
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra: sip_calls: fix defects flagged by MISRA scan ...

Main fixes:

* Expressions resulting from the expansion of macro parameters
  shall be enclosed in parentheses [Rule 20.7]
* Added explicit casts (e.g. 0U) to integers in order for them
  to be compatible with whatever operation they're used in [Rule
  10.1]
* Fix implicit widening of composite assignment [Rule 10.6]

Change-Id: Ia83c3ab6e4c8c03c19c950978a7936ebfc290590
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra186: secondary: fix MISRA defects ...

Main fixes:

Added explicit casts (e.g. 0U) to integers in order for them to be
compatible with whatever operation they're used in [Rule 10.1]

Force operands of an operator to the same type category [Rule 10.4]

Voided non c-library functions whose return types are not used [Rule 17.7]

Change-Id: I758e7ef6d45dd2edf4cd5580e2af15219246e75c
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

Tegra: Passing EKS size as boot arg to trusty ...

* EKS blob size was not passed by as a boot parameter
  earlier. Its being passed now
* If EKS value sent by bootloader is non-zero
  update the boot parameter from default value to the argument
  passed by bootloader

Change-Id: I65a3091bd2c1c908cc9e81c0aab6489cab02c098
Signed-off-by: Akshay Sharan <asharan@nvidia.com>

Tegra210B01: initialize DRBG on boot and resume ...

DRBG must be initialized to guarantee SRK has a random
value during suspend. This patch add a sequence to generate
an SRK on boot and during resume for SE1 and SE2. This SRK
value is not saved to PMC scratch, and should be overwitten
during atomic suspend.

Change-Id: Id5e2dc74a1b462dd6addaec1709fec46083a6e1c
Signed-off-by: Sam Payne <spayne@nvidia.com>

Tegra210: bpmp: power management interface ...

This patch adds the driver to communicate with the BPMP processor
for power management use cases. BPMP controls the entry into cluster
and system power states. The Tegra210 platform port queries the BPMP
to calculate the target state for the cluster. In case BPMP does not
allow CCx entry, the core enters a power down state.

Change-Id: I9c40aef561607a0b02c49b7f8118570eb9105cc9
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra186: mce: fix trivial MISRA defects ...

This patch fixes MISRA defects for the MCE driver.

* Using logical NOT for bool type function
* Using MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS replace
  MPIDR_CLUSTER_MASK

Change-Id: I97e96f172a3c1158646a15a184c273c53a103d63
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

Tegra: topology: fix MISRA defects for Rule 4.6 ...

This patch uses int32_t to replace ints, to fix Rule 4.6 of the
MISRA standard.

Change-Id: I20ac6185929eced684b43da3ef1f8cd5fbddc83d
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra: fiq_glue: fix MISRA defects for Rule 2.7 ...

This patch adds (void) for unused function parameters to
fix Rule 2.7 of the MISRA standard.

Change-Id: Ibc3f10b3bfe73363383b4c28413ab8d99fbc8c89
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra210B01: SE1 and SE2/PKA1 context save (atomic) ...

This patch adds the implementation of the SE atomic context save
sequence. The atomic context-save consistently saves to the TZRAM
carveout; thus there is no need to declare context save buffer or
map MMU region in TZRAM for context save. The atomic context-save
routine is responsible to validate the context-save progress
counter, where CTX_SAVE_CNT=133(SE1)/646(SE2), and the SE error
status to ensure the context save procedure complete successfully.

Change-Id: Ic80843902af70e76415530266cb158f668976c42
Signed-off-by: Marvin Hsu <marvinh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>