Add SPI-NOR framework ...

SPI-NOR framework is based on SPI-MEM framework using
spi_mem_op execution interface.

It implements read functions and allows NOR configuration
up to quad mode.
Default management is 1 data line but it can be overridden
by platform.
It also includes specific quad mode configuration for
Spansion, Micron and Macronix memories.

Change-Id: If49502b899b4a75f6ebc3190f6bde1013651197f
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>

Add SPI-NAND framework ...

This framework supports SPI-NAND and is based on the
SPI-MEM framework for SPI operations. It uses a common high
level access using the io_mtd.

It is limited to the read functionalities.

Default behavior is the basic one data line operation
but it could be overridden by platform.

Change-Id: Icb4e0887c4003a826f47c876479dd004a323a32b
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>

Add SPI-MEM framework ...

This framework supports SPI operations using a common
spi_mem_op structure:
 - command
 - addr
 - dummy
 - data

The framework manages SPI bus configuration:
 - speed
 - bus width (Up to quad mode)
 - chip select

Change-Id: Idc2736c59bfc5ac6e55429eba5d385275ea3fbde
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>

Add raw NAND framework ...

The raw NAND framework supports SLC NAND devices.

It introduces a new high level interface (io_mtd) that
defines operations a driver can register to the NAND framework.
This interface will fill in the io_mtd device specification:
	- device_size
        - erase_size
that could be used by the io_storage interface.

NAND core source file integrates the standard read loop that
performs NAND device read operations using a skip bad block strategy.
A platform buffer must be defined in case of unaligned
data. This buffer must fit to the maximum device page size
defined by PLATFORM_MTD_MAX_PAGE_SIZE.

The raw_nand.c source file embeds the specific NAND operations
to read data.
The read command is a raw page read without any ECC correction.
This can be overridden by a low level driver.
No generic support for write or erase command or software
ECC correction.

NAND ONFI detection is available and can be enabled using
NAND_ONFI_DETECT=1.
For non-ONFI NAND management, platform can define required
information.

Change-Id: Id80e9864456cf47f02b74938cf25d99261da8e82
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>

Merge changes from topic "ld/mtd_framework" into integration ...

* changes:
  io: change seek offset to signed long long
  compiler_rt: Import aeabi_ldivmode.S file and dependencies

Merge "zynqmp: pm: Add CLK_SET_RATE_PARENT in gem clock node" into integration

Merge changes from topic "add-versal-soc-support" into integration ...

* changes:
  zynqmp: pm: clock: Move custom flags to typeflags
  zynqmp: pm: clock: Add support for custom type flags
  plat: xilinx: zynqmp: Add GET_CALLBACK_DATA function
  zynqmp: pm: Remove CLK_TOPSW_LSBUS from invalid clock list

Merge "rcar_gen3: Add missing #{address,size}-cells into generated DT" into integration

Merge "docs: Creating a Change Log Template File" into integration

Merge "plat: intel: Fix UEFI decompression issue" into integration

Merge "intel: Change all global sip function to static" into integration

plat: intel: Fix UEFI decompression issue ...

UEFI decompression will fail if the payload size is too large and the load
address is too low. This patch moves the payload to a higher address to fix
the issue

Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
Change-Id: I36087fbd2237b62891c59dbe2d34336bddfaa396

intel: Change all global sip function to static ...

All function in socfpga_sip_svc.c should only be called locally except
sip_smc_handler().

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ib84ef9a2e521967baa4cfd32e6bc569dd3a5d2f5

Merge "a8k: Implement platform specific power off" into integration

Merge "allwinner: Reenable USE_COHERENT_MEM" into integration

allwinner: Reenable USE_COHERENT_MEM ...

Now that there is plenty of space (32 KiB) available for NOBITS
sections, we can afford using an entire page for coherent memory. In
fact, because it simplifies the code, this is a beneficial change for
loaded image (.text) size, where we are still close to the size limit.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I0b899dabcb162015c63b0e4aed0869569c889ed9

a8k: Implement platform specific power off ...

Implements a way to add platform specific power off code to a
Marvell Armada 8K platform.

Marvell Armada 8K boards can now add a board/system_power.c file
that contains a system_power_off() function.
This function can now send a command to a power management MCU or
other board periferals before shutting the board down.

Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Change-Id: Iaba20bc2f603195679c54ad12c0c18962dd8e3db
---
I am working on a device that will be ported later, which has a
custom power management MCU that handles LEDs, board power and fans
and requires this separation.

rcar_gen3: Add missing #{address,size}-cells into generated DT ...

Add missing #address-cells and #size-cells into generated DT, otherwise
the DT is invalid. While the parsers thus far handled this correctly via
various fallbacks, this is not applicable in the long run, so fix this.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ic808a3b27b93e5258ec1a19acc3d593e53625c15

zynqmp: pm: Add CLK_SET_RATE_PARENT in gem clock node ...

Existing implementation does not allow to change the value of the
DIV1 because DIV2 does not have SET_RATE_PARENT flag.
This causes DIV1 value to be fixed and only value of DIV2 will be
adjusted according to required clock rate.

Signed-off-by: Ravi Patel <ravi.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Ic6c4ca091bf0c5dc91ebddf86621c82c705dc87b

zynqmp: pm: clock: Move custom flags to typeflags ...

Linux expects custom flags in type flags. So move
custom flags to type flags instead of providing
them to clock core flags.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I668a8084d966815a9d9e86c2b18ecb5b18cb6b78

zynqmp: pm: clock: Add support for custom type flags ...

Add support to add extra custom type flags and provide
to caller in topology query.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Id9cc065dbadfed2291dd4f62674d7838da4cdf40

plat: xilinx: zynqmp: Add GET_CALLBACK_DATA function ...

Add GET_CALLBACK_DATA function again as now Linux driver
supports both mailbox as well as ISR method.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Ieb99d61976e1cb718fcd1021d9cf4958e7556c81

Merge changes from topic "sip-svc" into integration ...

* changes:
  intel: Implement platform specific system reset 2
  intel: Enable SiP SMC secure register access

Merge "uniphier: call uniphier_scp_is_running() only when on-chip STM is supported" into integration

Merge "intel: Fix memory calibration" into integration

Merge "rpi4: Fix documentation of armstub config entry" into integration

rpi4: Fix documentation of armstub config entry ...

It's in fact mandatory. Seen with RPi firmware 1.20190925.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Change-Id: I80739b74f25817294adc52cfd26a3ec59c06f892

Merge "plat: rpi4: Skip UART initialisation" into integration

Merge "console: 16550: Prepare for skipping initialisation" into integration

Merge changes from topic "add-versal-soc-support" into integration ...

* changes:
  zynqmp: pm: Add LPD WDT clock to the pm_clock structure
  zynqmp: pm: Fix clock models and IDs of GEM-related clocks
  zynqmp: pm: Rename FPD WDT clock ID
  plat: xilinx: zynqmp: Correct syscnt freq for QEMU
  arm64: zynqmp: Add idcodes for new RFSoC silicons ZU48DR and ZU49DR
  arm64: zynqmp: Add id for new RFSoC device ZU39DR