LuminaSensum/arm-trusted-firmware

Fork: 0

LuminaSensum / arm-trusted-firmware

History for arm-trusted-firmware / plat / intel / soc

2020-01-28	ca661a0 Browse files » Enable -Wredundant-decls warning check ... This flag warns if anything is declared more than once in the same scope, even in cases where multiple declaration is valid and changes nothing. Consequently, this patch also fixes the issues reported by this flag. Consider the following two lines of code from two different source files(bl_common.h and bl31_plat_setup.c): IMPORT_SYM(uintptr_t, __RO_START__, BL_CODE_BASE); IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE); The IMPORT_SYM macro which actually imports a linker symbol as a C expression. The macro defines the __RO_START__ as an extern variable twice, one for each instance. __RO_START__ symbol is defined by the linker script to mark the start of the Read-Only area of the memory map. Essentially, the platform code redefines the linker symbol with a different (relevant) name rather than using the standard symbol. A simple solution to fix this issue in the platform code for redundant declarations warning is to remove the second IMPORT_SYM and replace it with following assignment static const unsigned long BL2_RO_BASE = BL_CODE_BASE; Change-Id: If4835d1ee462d52b75e5afd2a59b64828707c5aa Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com> Madhukar Pappireddy committed on 28 Jan 2020
2020-01-24	dc2d366 Browse files » intel: Unify Platform specific defines for PSCI module ... PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: Id3d3efc7e7711d19f0223da823713b8390ad2f47 Deepika Bhavnani authored on 13 Dec 2019 Soby Mathew committed on 24 Jan 2020
2020-01-15	f2decc7 Browse files » intel: Add function to check fpga readiness ... Create a function to check for fpga readiness, and move the checking out of bridge enable function. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I3f473ffeffa9ce181a48977560c8bda19c6123c0 Hadi Asyrafi authored on 24 Dec 2019 Abdul Halim, Muhammad Hadi Asyrafi committed on 15 Jan 2020
	9c8f3af Browse files » intel: Add bridge control for FPGA reconfig ... This is to make sure that bridge access in disabled before doing full FPGA reconfiguration and turn re-enable it once the configuration succeed. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I1f42fbf04ac1625048bbdf21b8a0443464ed833d Hadi Asyrafi authored on 23 Dec 2019 Abdul Halim, Muhammad Hadi Asyrafi committed on 15 Jan 2020
	dfdd38c Browse files » intel: FPGA config_isdone() status query ... SiP CONFIG_ISDONE now will query status for either CONFIG_STATUS or RECONFIG_STATUS based on passed parameter Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Idb8a84af4e98654759843de09a289d31246c9a91 Hadi Asyrafi authored on 17 Dec 2019 Abdul Halim, Muhammad Hadi Asyrafi committed on 15 Jan 2020
	20335ca Browse files » intel: System Manager refactoring ... Refactored system manager driver to be shared across both intel platform Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ic4d056c3d15c3152403dc11641c2452770a6162d Hadi Asyrafi authored on 23 Dec 2019 Abdul Halim, Muhammad Hadi Asyrafi committed on 15 Jan 2020
	391eeee Browse files » intel: Refactor reset manager driver ... Refactor reset manager into intel common platform directory as it can be shared by both Stratix 10 and Agilex. Register address and field is now referred through macros. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Id6d50f2a2f5a6bd8d6746b84602ac17ec7f6c07a Hadi Asyrafi authored on 23 Dec 2019 Abdul Halim, Muhammad Hadi Asyrafi committed on 15 Jan 2020
	3dcb94d Browse files » intel: Enable bridge access in Intel platform ... Add bridge enablement features for each platform. The bridge access will be enabled automatically for FPGA 1st configuration only. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I264757b257a209e1c3c4206660f21c5d67af0d2f Hadi Asyrafi authored on 21 Oct 2019 Abdul Halim, Muhammad Hadi Asyrafi committed on 15 Jan 2020
	222519a Browse files » intel: Modify non secure access function ... Combine both peripheral and bridge non-secure access code into a single callable function Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I38d335ed8d1e9f55d337b63cca121a473897ef70 Hadi Asyrafi authored on 21 Oct 2019 Abdul Halim, Muhammad Hadi Asyrafi committed on 15 Jan 2020
	5d3ee07 Browse files » Merge "plat: intel: Fix UEFI decompression issue" into integration Manish Pandey authored on 15 Jan 2020 TrustedFirmware Code Review committed on 15 Jan 2020
	389091a Browse files » plat: intel: Fix UEFI decompression issue ... UEFI decompression will fail if the payload size is too large and the load address is too low. This patch moves the payload to a higher address to fix the issue Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com> Change-Id: I36087fbd2237b62891c59dbe2d34336bddfaa396 Tien Hock, Loh authored on 14 Oct 2019 Manish Pandey committed on 15 Jan 2020
	e5ebe87 Browse files » intel: Change all global sip function to static ... All function in socfpga_sip_svc.c should only be called locally except sip_smc_handler(). Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ib84ef9a2e521967baa4cfd32e6bc569dd3a5d2f5 Hadi Asyrafi authored on 17 Dec 2019 Manish Pandey committed on 15 Jan 2020
2020-01-14	e9ed7fa Browse files » Merge changes from topic "sip-svc" into integration ... * changes: intel: Implement platform specific system reset 2 intel: Enable SiP SMC secure register access Manish Pandey authored on 14 Jan 2020 TrustedFirmware Code Review committed on 14 Jan 2020
2020-01-14	bc3579b Browse files » Merge "intel: Fix memory calibration" into integration Manish Pandey authored on 14 Jan 2020 TrustedFirmware Code Review committed on 14 Jan 2020
2020-01-13	f6c4b19 Browse files » intel: Remove un-needed checks for qspi driver r/w ... This patch removes un-needed r/w parameter checks for qspi driver. The driver can actually access any offset and size. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: If60b2c016aa91e2c24ddc57c6ad410c8dc5dcf53 Hadi Asyrafi committed on 13 Jan 2020
2020-01-08	7a05f06 Browse files » Remove redundant declarations. ... In further patches, we wish to enable -wredundant-decls check as part of warning flags by default. Change-Id: I43410d6dbf40361a503c16d94ccf0f4cf29615b7 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com> Madhukar Pappireddy committed on 8 Jan 2020
2019-12-29	3d9f726 Browse files » intel: Fix memory calibration ... Increase calibration delay to cater for HPS 1st mode and reduce clear emif delay which takes too long Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I1a50a5d8a6518ba085d853cb636efa07326552b4 Hadi Asyrafi committed on 29 Dec 2019
	32cf34a Browse files » intel: Implement platform specific system reset 2 ... Add support for platform specific warm-reset through psci system reset 2. - system_reset2 implementation that calls for l2 cache reset - Check for magic number and request for warm reset in bl2 - Create a shared reset manager header file for Agilex and Stratix 10 - Clean up parameter info in plat_get_next_bl_params Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I3fdd9a2711c80d9bd3dc05b81527781d840bd726 Hadi Asyrafi committed on 29 Dec 2019
	13d33d5 Browse files » intel: Enable SiP SMC secure register access ... Enable access to secure registers by non-secure world through secure monitor calls Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I80610e08c7cf31f17f47a7597c269131a8de2491 Hadi Asyrafi committed on 29 Dec 2019
2019-12-19	aeb3d83 Browse files » Merge changes from topic "mailbox-fixes" into integration ... * changes: intel: Fix SMC SIP service intel: Introduce mailbox response length handling intel: Fix mailbox config return status intel: Mailbox driver logic fixes plat: intel: Fix FPGA manager on reconfiguration plat: intel: Fix mailbox send_cmd issue intel: Modify mailbox's get_config_status Manish Pandey authored on 19 Dec 2019 TrustedFirmware Code Review committed on 19 Dec 2019
2019-12-18	98ee29c Browse files » Merge "intel: Create SiP service header file" into integration Manish Pandey authored on 18 Dec 2019 TrustedFirmware Code Review committed on 18 Dec 2019
2019-12-17	7c58fd4 Browse files » intel: Fix SMC SIP service ... Fix FPGA reconfiguration driver logic Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I0299c1a71f3456e9b441340314662494b8d3e4a0 Hadi Asyrafi committed on 17 Dec 2019
	96612fc Browse files » intel: Introduce mailbox response length handling ... Mailbox driver now handles variable response length Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ic96854fdaadaf48379c5de688392df974e1c99c3 Hadi Asyrafi committed on 17 Dec 2019
	b68ba6c Browse files » intel: Fix mailbox config return status ... Modify mailbox config return code to improve debugging. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I0a223291f4c5296203b3295a679a5857a446c692 Hadi Asyrafi committed on 17 Dec 2019
	8014a53 Browse files » intel: Mailbox driver logic fixes ... Fix mailbox driver urgent command handling, doorbell routine, and logic optimization. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: If536a383f449ca2a68d60274303ec24f92411505 Hadi Asyrafi committed on 17 Dec 2019
	cefb37e Browse files » plat: intel: Fix FPGA manager on reconfiguration ... Fixes the SiP Service driver that is responsible for FPGA reconfiguration. Also change the base address of FPGA reconfiguration to 0x400000. Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com> Change-Id: I2b84c12c85cd5fc235247131fec4916ed2fb56c8 Tien Hock, Loh authored on 30 Oct 2019 Hadi Asyrafi committed on 17 Dec 2019
	68dd5e1 Browse files » plat: intel: Fix mailbox send_cmd issue ... There are a few issues in mailbox that needs to be fixed. - Send doorbell after an indirect cmd - Do not ring doorbell when polling mailbox response as it should've been sent by send_cmd - remove unneeded cmd_free_offset check - Fix mailbox initialization - Fix get_config_status returning a wrong status when the status is busy - Add command length in mailbox command header Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com> Change-Id: If613e2ca889a540a616c62d69ad0086a7cd46536 Tien Hock, Loh authored on 30 Oct 2019 Hadi Asyrafi committed on 17 Dec 2019
2019-12-16	23f31d3 Browse files » intel: stratix10: Modify BL31 parameter handling ... Add-in support for handling BL31 parameter from non-BL2 image, ie. SPL Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I16118d791399f652b6d1093c10092935a3449c32 Hadi Asyrafi committed on 16 Dec 2019
	cf82aff Browse files » intel: Modify BL31 address mapping ... Load BL31 to DDR instead of On-Chip RAM for scalability. Also, make use of On-Chip RAM for BL31 specific variables filling down from handoff offset to reduce fragmentation Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ib64f48bd14f71e5fca2d406f4ede3386f2881099 Hadi Asyrafi committed on 16 Dec 2019
	2db1e76 Browse files » intel: stratix10: Enable uboot entrypoint support ... This patch will provide an entrypoint for uboot's spl into BL31. BL31 will also handle secondary cpu state during uboot's cold boot Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I661bdb782c2d793d5fc3c7f78dd7ff746e33b7a3 Hadi Asyrafi committed on 16 Dec 2019