2019-07-16 |
Merge changes from topic "jc/shift-overflow" into integration
...
* changes:
Enable -Wshift-overflow=2 to check for undefined shift behavior
Update base code to not rely on undefined overflow behaviour
Update hisilicon drivers to not rely on undefined overflow behaviour
Update synopsys drivers to not rely on undefined overflow behaviour
Update imx platform to not rely on undefined overflow behaviour
Update mediatek platform to not rely on undefined overflow behaviour
Update layerscape platform to not rely on undefined overflow behaviour
Update intel platform to not rely on undefined overflow behaviour
Update rockchip platform to not rely on undefined overflow behaviour
Update renesas platform to not rely on undefined overflow behaviour
Update meson platform to not rely on undefined overflow behaviour
Update marvell platform to not rely on undefined overflow behaviour
Soby Mathew
authored
on 16 Jul 2019
TrustedFirmware Code Review
committed
on 16 Jul 2019
|
2019-07-12 |
Merge "AArch64: Add 128-bit integer types definitions" into integration
Sandrine Bailleux
authored
on 12 Jul 2019
TrustedFirmware Code Review
committed
on 12 Jul 2019
|
Update base code to not rely on undefined overflow behaviour
...
This consists of ensuring that the left operand of each shift is
unsigned when the operation might overflow into the sign bit.
Change-Id: Iddd6f38139a4c6e500468b4fc48d04e0939f574e
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
Justin Chadwell
committed
on 12 Jul 2019
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2019-07-11 |
Merge "Aarch64: Fix SCTLR bit definitions" into integration
John Tsichritzis
authored
on 11 Jul 2019
TrustedFirmware Code Review
committed
on 11 Jul 2019
|
2019-07-10 |
AArch64: Add 128-bit integer types definitions
...
This patch adds 128-bit integer types int128_t and uint128_t
for "__int128" and "unsigned __int128" supported by GCC and
Clang for AArch64.
Change-Id: I0e646d026a5c12a09fd2c71dc502082052256a94
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Alexei Fedorov
committed
on 10 Jul 2019
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Aarch64: Fix SCTLR bit definitions
...
This patch removes incorrect SCTLR_V_BIT definition and adds
definitions for ARMv8.3-Pauth EnIB, EnDA and EnDB bits.
Change-Id: I1384c0a01f56f3d945833464a827036252c75c2e
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Alexei Fedorov
committed
on 10 Jul 2019
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Rename Cortex-Deimos to Cortex-A77
...
Change-Id: I755e4c42242d9a052570fd1132ca3d937acadb13
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
Balint Dobszay
committed
on 10 Jul 2019
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2019-07-04 |
Merge changes from topic "lw/n1_errata_fixes" into integration
...
* changes:
Removing redundant ISB instructions
Workaround for Neoverse N1 erratum 1275112
Workaround for Neoverse N1 erratum 1262888
Workaround for Neoverse N1 erratum 1262606
Workaround for Neoverse N1 erratum 1257314
Workaround for Neoverse N1 erratum 1220197
Workaround for Neoverse N1 erratum 1207823
Workaround for Neoverse N1 erratum 1165347
Workaround for Neoverse N1 erratum 1130799
Workaround for Neoverse N1 erratum 1073348
Sandrine Bailleux
authored
on 4 Jul 2019
TrustedFirmware Code Review
committed
on 4 Jul 2019
|
2019-07-02 |
Workaround for Neoverse N1 erratum 1262888
...
Neoverse N1 erratum 1262888 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined
CPUECTLR_EL1 system register, which disables the MMU hardware prefetcher.
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html
Change-Id: Ib733d748e32a7ea6a2783f3d5a9c5e13eee01105
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
lauwal01
committed
on 2 Jul 2019
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Workaround for Neoverse N1 erratum 1262606
...
Neoverse N1 erratum 1262606 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined
CPUACTLR_EL1 system register, which delays instruction fetch after
branch misprediction.
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html
Change-Id: Idd980e9d5310232d38f0ce272862e1fb0f02ce9a
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
lauwal01
committed
on 2 Jul 2019
|
Workaround for Neoverse N1 erratum 1257314
...
Neoverse N1 erratum 1257314 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined
CPUACTLR3_EL1 system register, which prevents parallel
execution of divide and square root instructions.
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html
Change-Id: I54f0f40ff9043efee40d51e796b92ed85b394cbb
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
lauwal01
committed
on 2 Jul 2019
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Workaround for Neoverse N1 erratum 1220197
...
Neoverse N1 erratum 1220197 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set two bits in the implementation defined
CPUECTLR_EL1 system register, which disables write streaming to the L2.
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html
Change-Id: I9c3373f1b6d67d21ee71b2b80aec5e96826818e8
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
lauwal01
committed
on 2 Jul 2019
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Workaround for Neoverse N1 erratum 1207823
...
Neoverse N1 erratum 1207823 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined
CPUACTLR2_EL1 system register.
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html
Change-Id: Ia932337821f1ef0d644db3612480462a8d924d21
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
lauwal01
committed
on 2 Jul 2019
|
Workaround for Neoverse N1 erratum 1165347
...
Neoverse N1 erratum 1165347 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set two bits in the implementation defined
CPUACTLR2_EL1 system register.
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html
Change-Id: I163d0ea00578245c1323d2340314cdc3088c450d
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
lauwal01
committed
on 2 Jul 2019
|
Workaround for Neoverse N1 erratum 1130799
...
Neoverse N1 erratum 1130799 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined
CPUACTLR2_EL1 system register.
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html
Change-Id: I252bc45f9733443ba0503fefe62f50fdea61da6d
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
lauwal01
committed
on 2 Jul 2019
|
Workaround for Neoverse N1 erratum 1073348
...
Neoverse N1 erratum 1073348 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined
CPUACTLR_EL1 system register, which disables static prediction.
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html
Change-Id: I674126c0af6e068eecb379a190bcf7c75dcbca8e
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
lauwal01
committed
on 2 Jul 2019
|
2019-06-28 |
Merge changes from topic "av/console-port" into integration
...
* changes:
qemu: use new console interface in aarch32
warp7: remove old console from makefile
Remove MULTI_CONSOLE_API flag and references to it
Console: removed legacy console API
Paul Beesley
authored
on 28 Jun 2019
TrustedFirmware Code Review
committed
on 28 Jun 2019
|
Remove MULTI_CONSOLE_API flag and references to it
...
The new API becomes the default one.
Change-Id: Ic1d602da3dff4f4ebbcc158b885295c902a24fec
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Ambroise Vincent
committed
on 28 Jun 2019
|
2019-06-26 |
n1sdp: add code for DDR ECC enablement and BL33 copy to DDR
...
N1SDP platform supports RDIMMs with ECC capability. To use the ECC
capability, the entire DDR memory space has to be zeroed out before
enabling the ECC bits in DMC620. Zeroing out several gigabytes of
memory from SCP is quite time consuming so functions are added that
zeros out the DDR memory from application processor which is
much faster compared to SCP. BL33 binary cannot be copied to DDR memory
before enabling ECC so this is also done by TF-A from IOFPGA-DDR3
memory to main DDR4 memory after ECC is enabled.
Original PLAT_PHY_ADDR_SPACE_SIZE was limited to 36-bits with which
the entire DDR space cannot be accessed as DRAM2 starts in base
0x8080000000. So these macros are redefined for all ARM platforms.
Change-Id: If09524fb65b421b7a368b1b9fc52c49f2ddb7846
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
Manoj Kumar
committed
on 26 Jun 2019
|
2019-06-19 |
Merge changes from topic "yg/clk_syscfg_dt" into integration
...
* changes:
fdts: stm32mp1: realign device tree files with internal devs
stm32mp1: increase device tree size to 20kB
stm32mp1: make dt_get_stdout_node_offset() static
stm32mp1: use unsigned values for SDMMC defines
stm32mp1: remove useless LIBFDT_SRCS from PLAT_BL_COMMON_SOURCES
stm32mp1: update doc for U-Boot compilation
stm32mp1: add general SYSCFG management
stm32mp1: move stm32_get_gpio_bank_clock() to private file
clk: stm32mp1: correctly handle Clock Spreading Generator
clk: stm32mp1: use defines for mask values in stm32mp1_clk_sel array
clk: stm32mp1: move oscillator functions to generic file
arch: add some defines for generic timer registers
John Tsichritzis
authored
on 19 Jun 2019
TrustedFirmware Code Review
committed
on 19 Jun 2019
|
2019-06-17 |
Merge changes If61ab215,I3e8b0251,I1757eee9,I81b48475,I46b445a7, ... into integration
...
* changes:
rcar_gen3: drivers: qos: Move QoS drivers out of staging
rcar_gen3: drivers: qos: V3M: Configure DBSC QoS from a table
rcar_gen3: drivers: qos: E3: Configure DBSC QoS from a table
rcar_gen3: drivers: qos: D3: Configure DBSC QoS from a table
rcar_gen3: drivers: qos: M3N: Configure DBSC QoS from a table
rcar_gen3: drivers: qos: M3W: Configure DBSC QoS from a table
rcar_gen3: drivers: qos: H3: Configure DBSC QoS from a table
rcar_gen3: drivers: qos: Add function to configure DBSC QoS settings from a table
rcar_gen3: drivers: qos: Fix checkpatch issues
rcar_gen3: drivers: qos: V3M: Drop useless comments
rcar_gen3: drivers: qos: V3M: Convert mstat table to uint64_t
rcar_gen3: drivers: qos: V3M: Factor out mstat fix into separate file
rcar_gen3: drivers: qos: V3M: Use common register definition
rcar_gen3: drivers: qos: E3: Drop extra level of nesting
rcar_gen3: drivers: qos: E3: Use common register definition
rcar_gen3: drivers: qos: D3: Replace ad-hoc register addresses with macros
rcar_gen3: drivers: qos: D3: Drop MD pin check
rcar_gen3: drivers: qos: D3: Make DBSC settings local to dbsc_setting()
rcar_gen3: drivers: qos: D3: Drop useless comments
rcar_gen3: drivers: qos: D3: Convert mstat table to uint64_t
rcar_gen3: drivers: qos: D3: Factor out mstat fix into separate file
rcar_gen3: drivers: qos: D3: Use common register definition
rcar_gen3: drivers: qos: M3N: Fix checkpatch issues
rcar_gen3: drivers: qos: M3N: Drop MD pin check
rcar_gen3: drivers: qos: M3N: Drop useless comments
rcar_gen3: drivers: qos: M3N: Drop extra level of nesting
rcar_gen3: drivers: qos: M3N: Use common register definition
rcar_gen3: drivers: qos: M3W: Fix checkpatch issues
rcar_gen3: drivers: qos: M3W: Drop MD pin check
rcar_gen3: drivers: qos: M3W: Drop useless comments
rcar_gen3: drivers: qos: M3W: Drop extra level of nesting
rcar_gen3: drivers: qos: M3W: Convert mstat table to uint64_t
rcar_gen3: drivers: qos: M3W: Factor out mstat fix into separate file
rcar_gen3: drivers: qos: M3W: Use common register definition
rcar_gen3: drivers: qos: H3: Fix checkpatch issues
rcar_gen3: drivers: qos: H3: Drop MD pin check
rcar_gen3: drivers: qos: H3: Drop useless comments
rcar_gen3: drivers: qos: H3: Drop extra level of nesting
rcar_gen3: drivers: qos: H3: Convert mstat table to uint64_t
rcar_gen3: drivers: qos: H3: Factor out mstat fix into separate file
rcar_gen3: drivers: qos: H3: Use common register definition
rcar_gen3: console: Convert to multi-console API
John Tsichritzis
authored
on 17 Jun 2019
TrustedFirmware Code Review
committed
on 17 Jun 2019
|
clk: stm32mp1: use defines for mask values in stm32mp1_clk_sel array
...
Rework the macro that eases the table definition: the src and msk fields
are now using MASK and SHIFT defines of each source register.
Some macros had then to be modified: _USART1_SEL, _ASS_SEL and _MSS_SEL to
_UART1_SEL, _AXIS_SEL, and _MCUS_SEL to match register fields.
Note: the mask for RCC_ASSCKSELR_AXISSRC is changed from 0x3 to 0x7
to reflect the size of the register field, even if there are only
3 possible clock sources.
The mask value is also corrected for QSPI and FMC clock selection.
Change-Id: I44114e3c1dd37b9fa1be1ba519611abd9a07764c
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Yann Gautier
committed
on 17 Jun 2019
|
clk: stm32mp1: move oscillator functions to generic file
...
Those functions are generic for parsing nodes from device tree
hence could be located in generic source file.
The oscillators description structure is also moved to STM32MP1 clock
driver, as it is no more used in stm32mp1_clkfunc and cannot be in a
generic file.
Change-Id: I93ba74f4eea916440fef9b160d306af1b39f17c6
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Yann Gautier
committed
on 17 Jun 2019
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arch: add some defines for generic timer registers
...
Those defines are used in STM32MP1 clock driver.
It is better to put them altogether with already defined registers.
Change-Id: I6f8ad8c2477b947af6f76283a4ef5c40212d0027
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Yann Gautier
committed
on 17 Jun 2019
|
2019-06-13 |
rcar_gen3: console: Convert to multi-console API
...
Convert the R-Car Gen3 platform and both SCIF and Log drivers
to multi-console API.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I18556973937d150b60453f9150d54ee612571e35
Marek Vasut
committed
on 13 Jun 2019
|
Fix type of cot_desc_ptr
...
The chain of trust description and the pointer pointing to its first
element were incompatible, thus requiring an explicit type cast for
the assignment.
- cot_desc was an array of
const pointers to const image descriptors.
- cot_desc_ptr was a const pointer to
(non-constant) pointers to const image descriptors.
Thus, trying to assign cot_desc to cot_desc_ptr (with no cast) would
generate the following compiler warning:
drivers/auth/tbbr/tbbr_cot.c:826:14: warning: initialization discards
‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers]
REGISTER_COT(cot_desc);
^~~~~~~~
Change-Id: Iae62dd1bdb43fe379e3843d96461d47cc2f68a06
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Sandrine Bailleux
committed
on 13 Jun 2019
|
2019-06-06 |
Neoverse N1: Introduce workaround for Neoverse N1 erratum 1315703
...
Neoverse N1 erratum 1315703 is a Cat A (rare) erratum [1], present in
older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined CPUACTLR2_EL1
system register, which will disable the load-bypass-store feature.
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdocpjdoc-466751330-1032/index.html
Change-Id: I5c708dbe0efa4daa0bcb6bd9622c5efe19c03af9
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara
committed
on 6 Jun 2019
|
2019-05-29 |
Merge "Cortex-A55: workarounds for errata 1221012" into integration
Paul Beesley
authored
on 29 May 2019
TrustedFirmware Code Review
committed
on 29 May 2019
|
2019-05-28 |
Cortex-A55: workarounds for errata 1221012
...
The workaround is added to the Cortex-A55 cpu specific file. The
workaround is disabled by default and have to be explicitly enabled by
the platform integrator.
Change-Id: I3e6fd10df6444122a8ee7d08058946ff1cc912f8
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Ambroise Vincent
committed
on 28 May 2019
|
2019-05-24 |
Add support for Branch Target Identification
...
This patch adds the functionality needed for platforms to provide
Branch Target Identification (BTI) extension, introduced to AArch64
in Armv8.5-A by adding BTI instruction used to mark valid targets
for indirect branches. The patch sets new GP bit [50] to the stage 1
Translation Table Block and Page entries to denote guarded EL3 code
pages which will cause processor to trap instructions in protected
pages trying to perform an indirect branch to any instruction other
than BTI.
BTI feature is selected by BRANCH_PROTECTION option which supersedes
the previous ENABLE_PAUTH used for Armv8.3-A Pointer Authentication
and is disabled by default. Enabling BTI requires compiler support
and was tested with GCC versions 9.0.0, 9.0.1 and 10.0.0.
The assembly macros and helpers are modified to accommodate the BTI
instruction.
This is an experimental feature.
Note. The previous ENABLE_PAUTH build option to enable PAuth in EL3
is now made as an internal flag and BRANCH_PROTECTION flag should be
used instead to enable Pointer Authentication.
Note. USE_LIBROM=1 option is currently not supported.
Change-Id: Ifaf4438609b16647dc79468b70cd1f47a623362e
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Alexei Fedorov
committed
on 24 May 2019
|