2019-08-01 |
doc: Suggest to use the latest version 8.3 of GCC
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At the time of writting, GCC 8.3-2019.03 is the latest version available
on developer.arm.com.
Switch to bare-metal toolchain (arm-eabi-) for AArch32. This allows to
have a finer control on the use of floating-point and SIMD instructions.
Change-Id: I4438401405eae1e5f6d531b0162e8fa06f69135e
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Louis Mayencourt
committed
on 1 Aug 2019
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2019-07-25 |
Merge "Romlib makefile refactoring and script rewriting" into integration
Soby Mathew
authored
on 25 Jul 2019
TrustedFirmware Code Review
committed
on 25 Jul 2019
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2019-07-24 |
Merge "rockchip: px30: support px30" into integration
Soby Mathew
authored
on 24 Jul 2019
TrustedFirmware Code Review
committed
on 24 Jul 2019
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2019-07-22 |
Romlib makefile refactoring and script rewriting
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The features of the previously existing gentbl, genvar and genwrappers
scripts were reimplemented in the romlib_generator.py Python script.
This resulted in more readable and maintainable code and the script
introduces additional features that help dependency handling in
makefiles. The assembly templates were separated from the script logic
and were collected in the 'templates' directory.
The targets and their dependencies were reorganized in the makefile and
the dependency handling of included index files is possible now.
Incremental build is available in case of modifying the index files.
Signed-off-by: Imre Kis <imre.kis@arm.com>
Change-Id: I79f65fab9dc5c70d1f6fc8f57b2a3009bf842dc5
Imre Kis
committed
on 22 Jul 2019
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2019-07-19 |
Merge "intel: Adds support for Agilex platform" into integration
Soby Mathew
authored
on 19 Jul 2019
TrustedFirmware Code Review
committed
on 19 Jul 2019
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2019-07-18 |
doc: Complete the storage abstraction layer doc
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Add uml sequence and class diagram to illustrate the behavior of the
storage abstraction layer.
Change-Id: I338262729f8034cc3d3eea1d0ce19cca973a91bb
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Louis Mayencourt
committed
on 18 Jul 2019
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2019-07-17 |
intel: Adds support for Agilex platform
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Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ib2ad2068abdf0b204c5cb021ea919581adaca4ef
Hadi Asyrafi
committed
on 17 Jul 2019
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2019-07-12 |
doc: Generate PlantUML diagrams automatically
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Currently we have some pre-rendered versions of certain diagrams
in SVG format. These diagrams have corresponding PlantUML source
that can be rendered automatically as part of the documentation
build, removing the need for any intermediate files.
This patch adds the Sphinx "plantuml" extension, replaces
references to the pre-rendered SVG files within the documents,
and finally removes the SVG files and helper script.
New requirements for building the docs are the
"sphinxcontrib-plantuml" Python module (added to the pip
requirements.txt file) and the Graphviz package (provides the
"dot" binary) which is in the Ubuntu package repositories.
Change-Id: I24b52ee40ff79676212ed7cff350294945f1b50d
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
Paul Beesley
committed
on 12 Jul 2019
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Merge "Remove references to old project name from common files" into integration
Sandrine Bailleux
authored
on 12 Jul 2019
TrustedFirmware Code Review
committed
on 12 Jul 2019
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Merge "Fix RST rendering problem" into integration
Sandrine Bailleux
authored
on 12 Jul 2019
TrustedFirmware Code Review
committed
on 12 Jul 2019
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2019-07-10 |
Rename Cortex-Deimos to Cortex-A77
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Change-Id: I755e4c42242d9a052570fd1132ca3d937acadb13
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
Balint Dobszay
committed
on 10 Jul 2019
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Remove references to old project name from common files
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The project has been renamed from "Arm Trusted Firmware (ATF)" to
"Trusted Firmware-A (TF-A)" long ago. A few references to the old
project name that still remained in various places have now been
removed.
This change doesn't affect any platform files. Any "ATF" references
inside platform files, still remain.
Change-Id: Id97895faa5b1845e851d4d50f5750de7a55bf99e
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
John Tsichritzis
committed
on 10 Jul 2019
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2019-07-09 |
Fix RST rendering problem
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Change-Id: Ic5aab23b549d0bf8e0f7053b46fd59243214aac1
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
John Tsichritzis
committed
on 9 Jul 2019
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rockchip: px30: support px30
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px30 is a Quad-core soc and Cortex-a53 inside.
This patch supports the following functions:
1. basic platform setup
2. power up/off cpus
3. suspend/resume cpus
4. suspend/resume system
5. reset system
6. power off system
Change-Id: I73d55aa978096c078242be921abe0ddca9e8f67e
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
XiaoDong Huang
committed
on 9 Jul 2019
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2019-07-08 |
docs: removing references to GitHub
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Change-Id: Ibdee91ad337ee362872924d93e82f5b5e47e63d9
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
John Tsichritzis
committed
on 8 Jul 2019
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2019-07-04 |
Merge changes from topic "lw/n1_errata_fixes" into integration
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* changes:
Removing redundant ISB instructions
Workaround for Neoverse N1 erratum 1275112
Workaround for Neoverse N1 erratum 1262888
Workaround for Neoverse N1 erratum 1262606
Workaround for Neoverse N1 erratum 1257314
Workaround for Neoverse N1 erratum 1220197
Workaround for Neoverse N1 erratum 1207823
Workaround for Neoverse N1 erratum 1165347
Workaround for Neoverse N1 erratum 1130799
Workaround for Neoverse N1 erratum 1073348
Sandrine Bailleux
authored
on 4 Jul 2019
TrustedFirmware Code Review
committed
on 4 Jul 2019
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2019-07-02 |
Workaround for Neoverse N1 erratum 1275112
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Neoverse N1 erratum 1275112 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined
CPUACTLR_EL1 system register, which delays instruction fetch after
branch misprediction.
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html
Change-Id: If7fe55fe92e656fa6aea12327ab297f2e6119833
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
lauwal01
committed
on 2 Jul 2019
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Workaround for Neoverse N1 erratum 1262888
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Neoverse N1 erratum 1262888 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined
CPUECTLR_EL1 system register, which disables the MMU hardware prefetcher.
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html
Change-Id: Ib733d748e32a7ea6a2783f3d5a9c5e13eee01105
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
lauwal01
committed
on 2 Jul 2019
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Workaround for Neoverse N1 erratum 1262606
...
Neoverse N1 erratum 1262606 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined
CPUACTLR_EL1 system register, which delays instruction fetch after
branch misprediction.
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html
Change-Id: Idd980e9d5310232d38f0ce272862e1fb0f02ce9a
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
lauwal01
committed
on 2 Jul 2019
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Workaround for Neoverse N1 erratum 1257314
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Neoverse N1 erratum 1257314 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined
CPUACTLR3_EL1 system register, which prevents parallel
execution of divide and square root instructions.
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html
Change-Id: I54f0f40ff9043efee40d51e796b92ed85b394cbb
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
lauwal01
committed
on 2 Jul 2019
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Workaround for Neoverse N1 erratum 1220197
...
Neoverse N1 erratum 1220197 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set two bits in the implementation defined
CPUECTLR_EL1 system register, which disables write streaming to the L2.
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html
Change-Id: I9c3373f1b6d67d21ee71b2b80aec5e96826818e8
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
lauwal01
committed
on 2 Jul 2019
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Workaround for Neoverse N1 erratum 1207823
...
Neoverse N1 erratum 1207823 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined
CPUACTLR2_EL1 system register.
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html
Change-Id: Ia932337821f1ef0d644db3612480462a8d924d21
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
lauwal01
committed
on 2 Jul 2019
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Workaround for Neoverse N1 erratum 1165347
...
Neoverse N1 erratum 1165347 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set two bits in the implementation defined
CPUACTLR2_EL1 system register.
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html
Change-Id: I163d0ea00578245c1323d2340314cdc3088c450d
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
lauwal01
committed
on 2 Jul 2019
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Workaround for Neoverse N1 erratum 1130799
...
Neoverse N1 erratum 1130799 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined
CPUACTLR2_EL1 system register.
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html
Change-Id: I252bc45f9733443ba0503fefe62f50fdea61da6d
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
lauwal01
committed
on 2 Jul 2019
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Workaround for Neoverse N1 erratum 1073348
...
Neoverse N1 erratum 1073348 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined
CPUACTLR_EL1 system register, which disables static prediction.
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html
Change-Id: I674126c0af6e068eecb379a190bcf7c75dcbca8e
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
lauwal01
committed
on 2 Jul 2019
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2019-07-01 |
Merge changes from topic "banned_api_list" into integration
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* changes:
Fix the License header template in imx_aipstz.c
docs: Add the list of banned/use with caution APIs
Soby Mathew
authored
on 1 Jul 2019
TrustedFirmware Code Review
committed
on 1 Jul 2019
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docs: Add the list of banned/use with caution APIs
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Credit to sam.ellis@arm.com for the input to create the list.
Change-Id: Id70a8eddc5f2490811bebb278482c61950f10cce
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Soby Mathew
committed
on 1 Jul 2019
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2019-06-25 |
Merge "doc: Fix typo in file interrupt-framework-design.rst" into integration
John Tsichritzis
authored
on 25 Jun 2019
TrustedFirmware Code Review
committed
on 25 Jun 2019
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2019-06-24 |
Fix links in documentation
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Change-Id: Ifef4d634b4a34d23f42f61df5e326a1cc05d3844
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
John Tsichritzis
committed
on 24 Jun 2019
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2019-06-22 |
doc: Fix typo in file interrupt-framework-design.rst
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Signed-off-by: Peng Donglin <dolinux.peng@gmail.com>
Change-Id: I459e7d056735222f6f34e275dbdaf9a389d193fc
Peng Donglin
committed
on 22 Jun 2019
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