LuminaSensum/arm-trusted-firmware

Fork: 0

LuminaSensum / arm-trusted-firmware

History for arm-trusted-firmware / plat / intel / soc / stratix10 / bl2_plat_setup.c

2020-02-28	351d358 Browse files » Merge "intel: Enable EMAC PHY in Intel FPGA platform" into integration Sandrine Bailleux authored on 28 Feb 2020 TrustedFirmware Code Review committed on 28 Feb 2020
2020-02-25	98964f0 Browse files » 16550: Use generic console_t data structure ... Since now the generic console_t structure holds the UART base address as well, let's use that generic location and drop the UART driver specific data structure at all. Change-Id: I5c2fe3b6a667acf80c808cfec4a64059a2c9c25f Signed-off-by: Andre Przywara <andre.przywara@arm.com> Andre Przywara committed on 25 Feb 2020
2020-02-24	d603fd3 Browse files » intel: Enable EMAC PHY in Intel FPGA platform ... This initializes the EMAC PHY in both Stratix 10 and Agilex, without this, EMAC PHY wouldn't work correctly. Change-Id: I7e6b9e88fd9ef472884fcf648e6001fcb7549ae6 Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Tien Hock, Loh authored on 2 Oct 2019 Abdul Halim, Muhammad Hadi Asyrafi committed on 24 Feb 2020
2020-02-03	77fc469 Browse files » intel: Change boot source selection ... Platform handoff structure no longer includes boot source selection. Hence, those settings can now be configured through socfpga_plat_def.h. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: If7ec6a03bb25156a6670ebf8f77105c370b553f6 Hadi Asyrafi authored on 30 Dec 2019 Abdul Halim, Muhammad Hadi Asyrafi committed on 3 Feb 2020
2020-01-15	f2decc7 Browse files » intel: Add function to check fpga readiness ... Create a function to check for fpga readiness, and move the checking out of bridge enable function. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I3f473ffeffa9ce181a48977560c8bda19c6123c0 Hadi Asyrafi authored on 24 Dec 2019 Abdul Halim, Muhammad Hadi Asyrafi committed on 15 Jan 2020
	20335ca Browse files » intel: System Manager refactoring ... Refactored system manager driver to be shared across both intel platform Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ic4d056c3d15c3152403dc11641c2452770a6162d Hadi Asyrafi authored on 23 Dec 2019 Abdul Halim, Muhammad Hadi Asyrafi committed on 15 Jan 2020
	391eeee Browse files » intel: Refactor reset manager driver ... Refactor reset manager into intel common platform directory as it can be shared by both Stratix 10 and Agilex. Register address and field is now referred through macros. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Id6d50f2a2f5a6bd8d6746b84602ac17ec7f6c07a Hadi Asyrafi authored on 23 Dec 2019 Abdul Halim, Muhammad Hadi Asyrafi committed on 15 Jan 2020
	3dcb94d Browse files » intel: Enable bridge access in Intel platform ... Add bridge enablement features for each platform. The bridge access will be enabled automatically for FPGA 1st configuration only. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I264757b257a209e1c3c4206660f21c5d67af0d2f Hadi Asyrafi authored on 21 Oct 2019 Abdul Halim, Muhammad Hadi Asyrafi committed on 15 Jan 2020
2019-11-27	1520b5d Browse files » intel: Refactor common platform code [5/5] ... Removes unused source code for BL2 and BL31 in platform.mk. Clean-up unused header files, syntax fixes, and alphabetical sorting post-refactoring Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ie5ea9b4d3abdb0187cddeb04d2fcfb51fbe5c4dd Hadi Asyrafi committed on 27 Nov 2019
	d09adcb Browse files » intel: Refactor common platform code [3/5] ... Pull out mailbox driver into common area as they can be shared between intel's socfpga platform Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I4064de1ec668931d77abcb7804f6952b70d33716 Hadi Asyrafi committed on 27 Nov 2019
	e9b5e36 Browse files » intel: Refactor common platform code [2/5] ... Share socfpga private definitions and storage driver between Agilex and Stratix 10 platform. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I6da147f4d2df4a97c505d4bbcffadf63bc3bf4a5 Hadi Asyrafi committed on 27 Nov 2019
	328718f Browse files » intel: Refactor common platform code [1/5] ... Pull out handoff driver to intel/soc/ common directory as they can be shared by both Agilex and Stratix10 platform. Share platform_def header between both Agilex and Stratix10 and store platform specific definitions in socfpga_plat_def.h Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I8eff1afd7ee71704a36a54fad732ede4f557878d Hadi Asyrafi committed on 27 Nov 2019
2019-08-13	fea24b8 Browse files » intel: stratix10: Fix reliance on hard coded clock information ... Extract clock information for UART, MMC & Watchdog from the platform rather than hard code it Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I2582bd34a6da97bd75d5ccba5f93840e65f26b03 Hadi Asyrafi committed on 13 Aug 2019
2019-08-07	3f7b149 Browse files » intel: Platform common code refactor ... Pull out common code from aarch64 and include Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I4d0f5e1bb01bcdacbedf8e6c359de594239b645f Hadi Asyrafi authored on 1 Aug 2019 Sandrine Bailleux committed on 7 Aug 2019
2019-06-26	bf719f6 Browse files » intel: Pull out common drivers into platform common ... Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ib79e2c6fe6e66dec5004701133ad6a5f4c78f2fa Hadi Asyrafi committed on 26 Jun 2019
2019-03-20	10e70f8 Browse files » intel: Enable watchdog timer on Intel S10 platform ... Watchdog driver support & enablement during platform setup Signed-off-by: Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@intel.com> Muhammad Hadi Asyrafi Abdul Halim committed on 20 Mar 2019
2019-03-12	f5ba408 Browse files » intel: QSPI boot enablement ... Manages QSPI initialization, configuration and IO handling as boot device Signed-off-by: Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@intel.com> Muhammad Hadi Asyrafi Abdul Halim committed on 12 Mar 2019
2019-03-08	Unverified 3c652a2 Browse files » Merge pull request #1863 from thloh85-intel/mmc_fixes ... drivers: mmc: Fix some issues with MMC stack Dimitris Papastamos authored on 8 Mar 2019 GitHub committed on 8 Mar 2019
2019-03-07	dd8c03b Browse files » plat: intel: Add MMC OCR voltage information for initialization ... MMC stack needs OCR voltage information for the platform to initialize MMC controller correctly. Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com> Tien Hock, Loh committed on 7 Mar 2019
2019-03-07	5bd1b44 Browse files » intel: Mailbox service un-accessible ... Change map region for device 2 from non-secure to secure Signed-off-by: Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@intel.com> Muhammad Hadi Asyrafi Abdul Halim committed on 7 Mar 2019
2019-02-13	51f366a Browse files » plat: intel: Fix faulty DDR calibration value ... A DDR calibration value is missing write mask, causing ECC DDR calibration to fail. This patch addresses the issue. ECC should also be scrubbed before MMU initializes, thus the scrubbing is moved to ddr intialization phase. Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com> Loh Tien Hock committed on 13 Feb 2019
2019-02-04	9d82ef2 Browse files » plat: intel: Add BL2 support for Stratix 10 SoC ... This adds BL2 support for Intel Stratix 10 SoC FPGA. Functionality includes: - Release and setup peripherals from reset - Calibrate DDR - ECC DDR Scrubbing - Load FIP (bl31 and bl33) Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com> Loh Tien Hock committed on 4 Feb 2019