LuminaSensum/arm-trusted-firmware

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History for arm-trusted-firmware / plat / intel / soc

2020-01-08	7a05f06 Browse files » Remove redundant declarations. ... In further patches, we wish to enable -wredundant-decls check as part of warning flags by default. Change-Id: I43410d6dbf40361a503c16d94ccf0f4cf29615b7 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com> Madhukar Pappireddy committed on 8 Jan 2020
2019-12-29	3d9f726 Browse files » intel: Fix memory calibration ... Increase calibration delay to cater for HPS 1st mode and reduce clear emif delay which takes too long Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I1a50a5d8a6518ba085d853cb636efa07326552b4 Hadi Asyrafi committed on 29 Dec 2019
	32cf34a Browse files » intel: Implement platform specific system reset 2 ... Add support for platform specific warm-reset through psci system reset 2. - system_reset2 implementation that calls for l2 cache reset - Check for magic number and request for warm reset in bl2 - Create a shared reset manager header file for Agilex and Stratix 10 - Clean up parameter info in plat_get_next_bl_params Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I3fdd9a2711c80d9bd3dc05b81527781d840bd726 Hadi Asyrafi committed on 29 Dec 2019
	13d33d5 Browse files » intel: Enable SiP SMC secure register access ... Enable access to secure registers by non-secure world through secure monitor calls Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I80610e08c7cf31f17f47a7597c269131a8de2491 Hadi Asyrafi committed on 29 Dec 2019
2019-12-19	aeb3d83 Browse files » Merge changes from topic "mailbox-fixes" into integration ... * changes: intel: Fix SMC SIP service intel: Introduce mailbox response length handling intel: Fix mailbox config return status intel: Mailbox driver logic fixes plat: intel: Fix FPGA manager on reconfiguration plat: intel: Fix mailbox send_cmd issue intel: Modify mailbox's get_config_status Manish Pandey authored on 19 Dec 2019 TrustedFirmware Code Review committed on 19 Dec 2019
2019-12-18	98ee29c Browse files » Merge "intel: Create SiP service header file" into integration Manish Pandey authored on 18 Dec 2019 TrustedFirmware Code Review committed on 18 Dec 2019
2019-12-17	7c58fd4 Browse files » intel: Fix SMC SIP service ... Fix FPGA reconfiguration driver logic Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I0299c1a71f3456e9b441340314662494b8d3e4a0 Hadi Asyrafi committed on 17 Dec 2019
	96612fc Browse files » intel: Introduce mailbox response length handling ... Mailbox driver now handles variable response length Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ic96854fdaadaf48379c5de688392df974e1c99c3 Hadi Asyrafi committed on 17 Dec 2019
	b68ba6c Browse files » intel: Fix mailbox config return status ... Modify mailbox config return code to improve debugging. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I0a223291f4c5296203b3295a679a5857a446c692 Hadi Asyrafi committed on 17 Dec 2019
	8014a53 Browse files » intel: Mailbox driver logic fixes ... Fix mailbox driver urgent command handling, doorbell routine, and logic optimization. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: If536a383f449ca2a68d60274303ec24f92411505 Hadi Asyrafi committed on 17 Dec 2019
	cefb37e Browse files » plat: intel: Fix FPGA manager on reconfiguration ... Fixes the SiP Service driver that is responsible for FPGA reconfiguration. Also change the base address of FPGA reconfiguration to 0x400000. Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com> Change-Id: I2b84c12c85cd5fc235247131fec4916ed2fb56c8 Tien Hock, Loh authored on 30 Oct 2019 Hadi Asyrafi committed on 17 Dec 2019
	68dd5e1 Browse files » plat: intel: Fix mailbox send_cmd issue ... There are a few issues in mailbox that needs to be fixed. - Send doorbell after an indirect cmd - Do not ring doorbell when polling mailbox response as it should've been sent by send_cmd - remove unneeded cmd_free_offset check - Fix mailbox initialization - Fix get_config_status returning a wrong status when the status is busy - Add command length in mailbox command header Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com> Change-Id: If613e2ca889a540a616c62d69ad0086a7cd46536 Tien Hock, Loh authored on 30 Oct 2019 Hadi Asyrafi committed on 17 Dec 2019
2019-12-16	23f31d3 Browse files » intel: stratix10: Modify BL31 parameter handling ... Add-in support for handling BL31 parameter from non-BL2 image, ie. SPL Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I16118d791399f652b6d1093c10092935a3449c32 Hadi Asyrafi committed on 16 Dec 2019
	cf82aff Browse files » intel: Modify BL31 address mapping ... Load BL31 to DDR instead of On-Chip RAM for scalability. Also, make use of On-Chip RAM for BL31 specific variables filling down from handoff offset to reduce fragmentation Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ib64f48bd14f71e5fca2d406f4ede3386f2881099 Hadi Asyrafi committed on 16 Dec 2019
	2db1e76 Browse files » intel: stratix10: Enable uboot entrypoint support ... This patch will provide an entrypoint for uboot's spl into BL31. BL31 will also handle secondary cpu state during uboot's cold boot Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I661bdb782c2d793d5fc3c7f78dd7ff746e33b7a3 Hadi Asyrafi committed on 16 Dec 2019
	ec7d005 Browse files » intel: Modify mailbox's get_config_status ... Move the get_config_status out of sip_svc driver. Modify the function so that it can return either CONFIG_STATUS or RECONFIG_STATUS Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I642d5900339e67f98be61380edc2b838e0dd47af Hadi Asyrafi committed on 16 Dec 2019
	d25041b Browse files » intel: Create SiP service header file ... Separate SiP related definition from mailbox header file Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I45ba540f29d9261007f7ec23469358747cf140b4 Hadi Asyrafi committed on 16 Dec 2019
2019-12-11	0d1b704 Browse files » intel: s10: Remove unused source code ... remove plat_sip_svc.c and plat_psci.c in stratix 10 platform directory as both has been refactored to common directory for sharing with agilex platform Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I395fed66408f536e8fefd637681e742c63621818 Hadi Asyrafi committed on 11 Dec 2019
2019-11-27	1520b5d Browse files » intel: Refactor common platform code [5/5] ... Removes unused source code for BL2 and BL31 in platform.mk. Clean-up unused header files, syntax fixes, and alphabetical sorting post-refactoring Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ie5ea9b4d3abdb0187cddeb04d2fcfb51fbe5c4dd Hadi Asyrafi committed on 27 Nov 2019
	c76d423 Browse files » intel: Refactor common platform code [4/5] ... Pull out SiP & PSCI service driver into socfpga common directory. Remove deassert_peripheral_reset from cold reset procedure as it is not needed. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I1a0390fca6db4c89919a2a038de2a9d96c3ae4fd Hadi Asyrafi committed on 27 Nov 2019
	d09adcb Browse files » intel: Refactor common platform code [3/5] ... Pull out mailbox driver into common area as they can be shared between intel's socfpga platform Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I4064de1ec668931d77abcb7804f6952b70d33716 Hadi Asyrafi committed on 27 Nov 2019
	e9b5e36 Browse files » intel: Refactor common platform code [2/5] ... Share socfpga private definitions and storage driver between Agilex and Stratix 10 platform. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I6da147f4d2df4a97c505d4bbcffadf63bc3bf4a5 Hadi Asyrafi committed on 27 Nov 2019
	328718f Browse files » intel: Refactor common platform code [1/5] ... Pull out handoff driver to intel/soc/ common directory as they can be shared by both Agilex and Stratix10 platform. Share platform_def header between both Agilex and Stratix10 and store platform specific definitions in socfpga_plat_def.h Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I8eff1afd7ee71704a36a54fad732ede4f557878d Hadi Asyrafi committed on 27 Nov 2019
2019-09-12	b90f207 Browse files » Invalidate dcache build option for bl2 entry at EL3 ... Some of the platform (ie. Agilex) make use of CCU IPs which will only be initialized during bl2_el3_early_platform_setup. Any operation to the cache beforehand will crash the platform. Hence, this will provide an option to skip the data cache invalidation upon bl2 entry at EL3 Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I2c924ed0589a72d0034714c31be8fe57237d1f06 Hadi Asyrafi authored on 20 Aug 2019 Soby Mathew committed on 12 Sep 2019
2019-09-12	afac968 Browse files » intel: agilex: Fix psci power domain off ... Disable gic cpu interface for powered down cpu. This patch also removes core reset during power off as core reset will be done during power on Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I2ca96d876b6e71e56d24a9a7e184b6d6226b8673 Hadi Asyrafi committed on 12 Sep 2019
2019-09-05	5dbdf8e Browse files » Merge "intel: stratix10: Fix reliance on hard coded clock information" into integration Sandrine Bailleux authored on 5 Sep 2019 TrustedFirmware Code Review committed on 5 Sep 2019
2019-08-28	3441952 Browse files » Merge "intel: agilex: Clear PLL lostlock bypass mode" into integration Paul Beesley authored on 28 Aug 2019 TrustedFirmware Code Review committed on 28 Aug 2019
2019-08-19	24d16a2 Browse files » intel: agilex: HMC driver calculate DDR size ... Driver will calculate DDR size instead of using hardcoded value Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I642cf2180929965ef12bd5ae4393b2f3d0dcddde Hadi Asyrafi committed on 19 Aug 2019
2019-08-18	960a12b Browse files » intel: agilex: Clear PLL lostlock bypass mode ... To provide glitchless clock to downstream logic even if clock toggles Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I728d64d0ba3b4492125bea5b0737fc83180356f1 Hadi Asyrafi committed on 18 Aug 2019
2019-08-15	d1b6013 Browse files » Merge "intel: agilex: Fix memory controller driver" into integration Paul Beesley authored on 15 Aug 2019 TrustedFirmware Code Review committed on 15 Aug 2019