treewide: make use of PTR_ERR_OR_ZERO ...

PTR_ERR_OR_ZERO is designed to replace boiler plate like:

	if (IS_ERR(x))
		return PTR_ERR(x);
	return 0;

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/kbuild'

drivers: add COMPILE_TEST prompts for some off-by-default options ...

Some Kconfig options we have are promptless and off-by-default and
instead can only be enabled by being selected from platform options.

For some of those that aren't compile testable, add a new
COMPILE_TEST-only prompt.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

drivers: mark first batch of compilable drivers for COMPILE_TEST ...

All of these drivers have a runtime dependency on SoC peripherals, but
can nevertheless be compile-tested. Add COMPILE_TEST as an alternate
dependency.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

kbuild: support ccflags-y, asflags-y, cppflags-y, and ldflags-y ...

Some Makefiles use ccflags-y, but it is not actually supported.
Support ccflags-y, asflags-y, cppflags-y, and ldflags-y like Linux.

Remove the workaround in drivers/pci/Makefile.

Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: layerscape: be less noisy when no iommu node is found ...

The upstream device tree files do not have the iommu nodes and
properties, so do not complain too loudly when they are not found.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: layerscape: Allow to share stream_ids per host controller ...

Normally every device gets its own stream_id. The stream_ids are
communicated to the kernel in the device tree and are also configured
in the controllers LUT table.

This only works when all PCI devices are known in the bootloader
which may not always be the case. For example, when a PCI device
is a FPGA and its firmware is only loaded under Linux, then the
device is not known to barebox and thus not assigned a stream_id.

With global.layerscape_pcie.share_stream_ids set to true all devices
on a host controller get the same stream_id assigned. This setup is
completely device agnostic and thus also works when not all devices
are known to barebox.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: layerscape: Fixup iommu-map properties ...

The iommu-map properties are needed for proper PCI support under Linux.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: layerscape: rename variable ...

Rename 'arr' to 'msi_map' which is a better name when we add another
array in the next patch.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: copy over some Linux PCI helpers ...

Linux PCI drivers, like the incoming 8250_pci, make use of these
helpers. Port them over from Linux v5.4.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: Add layerscape PCIe driver ...

This adds support for the designware based PCIe controller found on
Layerscape SoCs. The driver is based on Linux-5.4. The device tree
fixups have been taken from U-Boot 2019.10.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: Return directly when num-lanes is not found ...

Port of Linux commit 66de33f

    The num-lanes is optional since it is not needed on some platforms
    that bring up the link in firmware.

    The link programming is based on the num-lanes properties (which is
    optional); if it is not present code must return instead of fiddling
    with the lanes value to print an error message.

    Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
    Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
    Reviewed-by: Andrew Murray <andrew.murray@arm.com>

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: Sync register definitions with Linux-5.4 ...

Update the dwc register definitions with Linux-5.4 to make further
syncinf with the Linux driver easier.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: rename readl/writel_dbi ops to read/write_dbi ...

struct dw_pcie_ops read/writel_dbi functions can read values of any
size, so with readl/writel they are misnamed. Rename them to read/write
which also matches the kernel driver.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: Cleanup DBI,ATU read and write APIs ...

Port of Linux commit 7bc082d

    Cleanup DBI read and write APIs by removing leading "__" (underscore)
    from their names as there is no reason to have leading underscores
    in the first place in the function definition.

    Remove dbi/dbi2 base address parameters as the same behaviour can be
    obtained through read and write APIs. Since dw_pcie_{readl/writel}_dbi()
    APIs can't be used for ATU read/write as ATU base address could be
    different from DBI base address, implement ATU read/write APIs using ATU
    base address without using dw_pcie_{readl/writel}_dbi() APIs.

    Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
    Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
    Acked-by: Jingoo Han <jingoohan1@gmail.com>

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: imx6: Share PHY debug register definitions ...

Port of Linux commit 60ef4b0

    Both pcie-designware.c and pci-imx6.c contain custom definitions for
    PHY debug registers R0/R1 and on top of that there's already a
    definition for R0 in pcie-designware.h. Move all of the definitions to
    pcie-designware.h. No functional change intended.

    Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
    Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
    Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
    Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
    Cc: Bjorn Helgaas <bhelgaas@google.com>
    Cc: Chris Healy <cphealy@gmail.com>
    Cc: Lucas Stach <l.stach@pengutronix.de>
    Cc: linux-kernel@vger.kernel.org
    Cc: linux-pci@vger.kernel.org

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: Fix ATU identification for designware version >= 4.80 ...

Port of Linux commit 2aadcb0

    Synopsys designware version >= 4.80 uses a separate register space
    for programming ATU. The current code identifies if there exists a
    separate register space by accessing the register address of ATUs
    in designware version < 4.80. Accessing this address results in
    abort in the case of K2G.

    Fix it here by adding "version" member to struct dw_pcie. This should be
    set by platform specific drivers and designware core will use it to
    identify if the platform has a separate ATU space. For platforms which
    have not populated the version member, the old method of identification
    will still be used.

    Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
    Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: Enable iATU unroll for endpoint too ...

Port of Linux commit a9f4c2d

    iatu_unroll_enabled flag is set only for Designware in host mode.

    However iATU unroll can be applicable for endpoint mode too. Set
    iatu_unroll_enabled flag in dw_pcie_setup() which is common for
    both host mode and endpoint mode.

    Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
    Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: Make use of BIT() in constant definitions ...

Port of Linux commit 0e11faa

    Avoid using explicit left shifts and convert various definitions to
    use BIT() instead. No functional change intended.

    Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
    [lorenzo.pieralisi@arm.com: fixed PORT_LOGIC_SPEED_CHANGE redefinition]
    Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
    Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
    Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
    Cc: Bjorn Helgaas <bhelgaas@google.com>
    Cc: Fabio Estevam <fabio.estevam@nxp.com>
    Cc: Chris Healy <cphealy@gmail.com>
    Cc: Lucas Stach <l.stach@pengutronix.de>
    Cc: Leonard Crestez <leonard.crestez@nxp.com>
    Cc: "A.s. Dong" <aisheng.dong@nxp.com>
    Cc: Richard Zhu <hongxing.zhu@nxp.com>
    Cc: linux-imx@nxp.com
    Cc: linux-arm-kernel@lists.infradead.org
    Cc: linux-kernel@vger.kernel.org
    Cc: linux-pci@vger.kernel.org

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: Add dw_pcie_disable_atu() ...

This adds dw_pcie_disable_atu() taken from Linux-5.4. This is needed by
the upcoming Layerscape driver.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: Make use of IS_ALIGNED() ...

Port of Linux commit 4f8bbd2

    Make the intent a bit more clear as well as get rid of explicit
    arithmetic by using IS_ALIGNED() to determine if "addr" is aligned to
    "size". No functional change intended.

    Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
    Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
    Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
    Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
    Cc: Bjorn Helgaas <bhelgaas@google.com>
    Cc: Fabio Estevam <fabio.estevam@nxp.com>
    Cc: Chris Healy <cphealy@gmail.com>
    Cc: Lucas Stach <l.stach@pengutronix.de>
    Cc: Leonard Crestez <leonard.crestez@nxp.com>
    Cc: "A.s. Dong" <aisheng.dong@nxp.com>
    Cc: Richard Zhu <hongxing.zhu@nxp.com>
    Cc: linux-imx@nxp.com
    Cc: linux-arm-kernel@lists.infradead.org
    Cc: linux-kernel@vger.kernel.org
    Cc: linux-pci@vger.kernel.org

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: dwc: Don't hard-code DBI/ATU offset ...

Port of Linux commit 6d6b05e

    The DWC PCIe core contains various separate register spaces: DBI, DBI2,
    ATU, DMA, etc. The relationship between the addresses of these register
    spaces is entirely determined by the implementation of the IP block, not
    by the IP block design itself. Hence, the DWC driver must not make
    assumptions that one register space can be accessed at a fixed offset from
    any other register space. To avoid such assumptions, introduce an
    explicit/separate register pointer for the ATU register space. In
    particular, the current assumption is not valid for NVIDIA's T194 SoC.

    The ATU register space is only used on systems that require unrolled ATU
    access. This property is detected at run-time for host controllers, and
    when this is detected, this patch provides a default value for atu_base
    that matches the previous assumption re: register layout. An alternative
    would be to update all drivers for HW that requires unrolled access to
    explicitly set atu_base. However, it's hard to tell which drivers would
    require atu_base to be set. The unrolled property is not detected for
    endpoint systems, and so any endpoint driver that requires unrolled access
    must explicitly set the iatu_unroll_enabled flag (none do at present), and
    so a check is added to require the driver to also set atu_base while at
    it.

    Signed-off-by: Stephen Warren <swarren@nvidia.com>
    Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
    Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
    Acked-by: Vidya Sagar <vidyas@nvidia.com>

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/misc'

PCI: dwc: tune down link up messages ...

This function may be called repeatedly while establishing the link,
so printing a message each time a working link is found can add quite
a bit of noise. Tune those messages down to the debug level.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: imx6: Add code to request/control "pcie_aux" clock for i.MX8MQ ...

Port of a Linux commit 29d6b80

  The PCIe IP block has an additional clock, "pcie_aux", that needs to
  be controlled by the driver. Add code to support it.

  Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
  Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
  Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
  Cc: Bjorn Helgaas <bhelgaas@google.com>
  Cc: Fabio Estevam <fabio.estevam@nxp.com>
  Cc: Chris Healy <cphealy@gmail.com>
  Cc: Lucas Stach <l.stach@pengutronix.de>
  Cc: Leonard Crestez <leonard.crestez@nxp.com>
  Cc: "A.s. Dong" <aisheng.dong@nxp.com>
  Cc: Richard Zhu <hongxing.zhu@nxp.com>
  Cc: linux-imx@nxp.com
  Cc: linux-arm-kernel@lists.infradead.org
  Cc: linux-kernel@vger.kernel.org
  Cc: linux-pci@vger.kernel.org
  Cc: Rob Herring <robh@kernel.org>
  Cc: devicetree@vger.kernel.org

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/pci'

Merge branch 'for-next/misc'

PCI: imx6: Add support for i.MX8MQ ...

Port of a Linux commit 2d8ed46

  Add code needed to support i.MX8MQ variant.

  Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
  Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
  Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
  Cc: Bjorn Helgaas <bhelgaas@google.com>
  Cc: Fabio Estevam <fabio.estevam@nxp.com>
  Cc: Chris Healy <cphealy@gmail.com>
  Cc: Lucas Stach <l.stach@pengutronix.de>
  Cc: Leonard Crestez <leonard.crestez@nxp.com>
  Cc: "A.s. Dong" <aisheng.dong@nxp.com>
  Cc: Richard Zhu <hongxing.zhu@nxp.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: imx6: Convert DIRECT_SPEED_CHANGE quirk code to use a flag ...

Port of a Linux commit 4c458bb

  Both i.MX7D and i.MX8MQ have the same behaviour when it comes to
  clearing DIRECT_SPEED_CHANGE bit when no speed change occurs, so to
  handle variants correctly add a flag instead of checking the IP block
  variant.

  Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
  [lorenzo.pieralisi@arm.com: updated log]
  Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
  Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
  Cc: Bjorn Helgaas <bhelgaas@google.com>
  Cc: Fabio Estevam <fabio.estevam@nxp.com>
  Cc: Chris Healy <cphealy@gmail.com>
  Cc: Lucas Stach <l.stach@pengutronix.de>
  Cc: Leonard Crestez <leonard.crestez@nxp.com>
  Cc: "A.s. Dong" <aisheng.dong@nxp.com>
  Cc: Richard Zhu <hongxing.zhu@nxp.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: imx6: Mark PHY functions as i.MX6 specific ...

Port of a Linux commit 2f532d0

  PCIe PHY IP block on i.MX7D differs from the one used on i.MX6 family,
  so none of the code in the current implementation of
  imx6_setup_phy_mpll() or imx6_pcie_reset_phy() is applicable.

  Introduce IMX6_PCIE_FLAG_IMX6_PHY and check for it in the aforementioned
  functions to make sure they are only executed on appropriate PCIe IP
  variants.

  Tested-by: Trent Piepho <tpiepho@impinj.com>
  Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
  [lorenzo.pieralisi@arm.com: updated log]
  Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
  Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
  Cc: Bjorn Helgaas <bhelgaas@google.com>
  Cc: Fabio Estevam <fabio.estevam@nxp.com>
  Cc: Chris Healy <cphealy@gmail.com>
  Cc: Lucas Stach <l.stach@pengutronix.de>
  Cc: Leonard Crestez <leonard.crestez@nxp.com>
  Cc: "A.s. Dong" <aisheng.dong@nxp.com>
  Cc: Richard Zhu <hongxing.zhu@nxp.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>