2019-02-27 |
Merge pull request #1831 from antonio-nino-diaz-arm/an/sccd
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Disable processor Cycle Counting in Secure state
Antonio Niño Díaz
authored
on 27 Feb 2019
GitHub
committed
on 27 Feb 2019
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2019-02-26 |
rpi3: sdhost: SDHost driver improvement
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This commit improves the SDHost driver for RPi3 as following:
* Unblock MMC_CMD(17). Using MMC_CMD(17) is more efficient on
block reading.
* In some low probability that SEND_OP_COND might results CRC7
error. We can consider that the command runs correctly. We don't
need to retry this command so removing the code for retry.
* Using MMC_BUS_WIDTH_1 as MMC default value to improve the stability.
* Increase the clock to 50Mhz in data mode to speed up the io.
* Change the pull resistors configuration to gain more stability.
Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Ying-Chun Liu (PaulLiu)
committed
on 26 Feb 2019
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Add workaround for errata 1073348 for Cortex-A76
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Concurrent instruction TLB miss and mispredicted return instruction
might fetch wrong instruction stream. Set bit 6 of CPUACTLR_EL1 to
prevent this.
Change-Id: I2da4f30cd2df3f5e885dd3c4825c557492d1ac58
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Louis Mayencourt
committed
on 26 Feb 2019
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Add workaround for errata 1220197 for Cortex-A76
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Streaming store under specific conditions might cause deadlock or data
corruption. Set bit 25:24 of CPUECTLR_EL1, which disables write
streaming to the L2 to prevent this.
Change-Id: Ib5cabb997b35ada78b27e75787afd610ea606dcf
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Louis Mayencourt
committed
on 26 Feb 2019
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Add workaround for errata 764081 of Cortex-A75
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Implicit Error Synchronization Barrier (IESB) might not be correctly
generated in Cortex-A75 r0p0. To prevent this, IESB are enabled at all
expection levels.
Change-Id: I2a1a568668a31e4f3f38d0fba1d632ad9939e5ad
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Louis Mayencourt
committed
on 26 Feb 2019
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Add workaround for errata 855423 of Cortex-A73
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Broadcast maintainance operations might not be correctly synchronized
between cores. Set bit 7 of S3_0_C15_C0_2 to prevent this.
Change-Id: I67fb62c0b458d44320ebaedafcb8495ff26c814b
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Louis Mayencourt
committed
on 26 Feb 2019
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2019-02-22 |
Merge pull request #1836 from Yann-lms/docs_and_m4
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Update documentation for STM32MP1 and add Cortex-M4 support
Antonio Niño Díaz
authored
on 22 Feb 2019
GitHub
committed
on 22 Feb 2019
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Merge pull request #1835 from jts-arm/rename
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Apply official names to new Arm Neoverse cores
Antonio Niño Díaz
authored
on 22 Feb 2019
GitHub
committed
on 22 Feb 2019
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2019-02-21 |
Merge pull request #1828 from uarif1/master
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Introduce Versatile Express FVP platform to arm-trusted-firmware.
Antonio Niño Díaz
authored
on 21 Feb 2019
GitHub
committed
on 21 Feb 2019
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2019-02-20 |
stm32mp1: add minimal support for co-processor Cortex-M4
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STM32MP1 chip embeds a dual Cortex-A7 and a Cortex-M4.
The support for Cortex-M4 clocks is added when configuring the clock tree.
Some minimal security features to allow communications between A7 and M4
are also added.
Change-Id: I60417e244a476f60a2758f4969700b2684056665
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Yann Gautier
committed
on 20 Feb 2019
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2019-02-19 |
plat/arm: Support for Cortex A5 in FVP Versatile Express platform
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Cortex A5 doesnt support VFP, Large Page addressing and generic timer
which are addressed in this patch. The device tree for Cortex a5
is also included.
Change-Id: I0722345721b145dfcc80bebd36a1afbdc44bb678
Signed-off-by: Usama Arif <usama.arif@arm.com>
Usama Arif
committed
on 19 Feb 2019
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Division functionality for cores that dont have divide hardware.
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Cortex a5 doesnt support hardware division such as sdiv and udiv commands.
This commit adds a software division function in assembly as well as include
appropriate files for software divison.
The software division algorithm is a modified version obtained from:
http://www.keil.com/support/man/docs/armasm/armasm_dom1359731155623.htm
Change-Id: Ib405a330da5f1cea1e68e07e7b520edeef9e2652
Signed-off-by: Usama Arif <usama.arif@arm.com>
Usama Arif
committed
on 19 Feb 2019
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ARMv7: support non-LPAE mapping (not xlat_v2)
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Support 32bit descriptor MMU table. This is required by ARMv7
architectures that do not support the Large Page Address Extensions.
nonlpae_tables.c source file is dumped from the OP-TEE project:
core_mmu_armv7.c and related header files.
Change-Id: If912d66c374290c49c5a1211ce4c5c27b2d7dc60
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Usama Arif <usama.arif@arm.com>
Etienne Carriere
authored
on 24 Oct 2017
Usama Arif
committed
on 19 Feb 2019
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Rename Cortex-Helios to Neoverse E1
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Change-Id: I1adcf195c0ba739002f3a59e805c782dd292ccba
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
John Tsichritzis
committed
on 19 Feb 2019
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Rename Cortex-Helios filenames to Neoverse E1
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Change-Id: I33bdb9df0462b056adbd00922b2e73eb720560b3
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
John Tsichritzis
committed
on 19 Feb 2019
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Rename Cortex-Ares to Neoverse N1
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Change-Id: Ideb49011da35f39ff1959be6f5015fa212ca2b6b
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
John Tsichritzis
committed
on 19 Feb 2019
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Rename Cortex-Ares filenames to Neoverse N1
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Change-Id: I0bb5aca9bb272332340b5baefc473a01f8a27896
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
John Tsichritzis
committed
on 19 Feb 2019
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Merge pull request #1825 from antonio-nino-diaz-arm/an/csv2
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Update macro to check need for CVE-2017-5715 mitigation
Antonio Niño Díaz
authored
on 19 Feb 2019
GitHub
committed
on 19 Feb 2019
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2019-02-18 |
Disable processor Cycle Counting in Secure state
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In a system with ARMv8.5-PMU implemented:
- If EL3 is using AArch32, setting MDCR_EL3.SCCD to 1 disables counting
in Secure state in PMCCNTR.
- If EL3 is using AArch64, setting SDCR.SCCD to 1 disables counting in
Secure state in PMCCNTR_EL0.
So far this effect has been achieved by setting PMCR_EL0.DP (in AArch64)
or PMCR.DP (in AArch32) to 1 instead, but this isn't considered secure
as any EL can change that value.
Change-Id: I82cbb3e48f2e5a55c44d9c4445683c5881ef1f6f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz
committed
on 18 Feb 2019
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Rename PLAT_ARM_BL31_RUN_UART* variable
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The variable is renamed to PLAT_ARM_RUN_UART as
the UART is used outside BL31 as well.
Change-Id: I00e3639dfb2001758b7d24548c11236c6335f64a
Signed-off-by: Usama Arif <usama.arif@arm.com>
Usama Arif
committed
on 18 Feb 2019
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2019-02-14 |
Update macro to check need for CVE-2017-5715 mitigation
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Armv8.5 introduces the field CSV2 to register ID_AA64PFR0_EL1. It can
have the following 3 values:
- 0: Branch targets trained in one hardware described context may affect
speculative execution in a different hardware described context. In
some CPUs it may be needed to apply mitigations.
- 1: Branch targets trained in one hardware described context can only
affect speculative execution in a different hardware described
context in a hard-to-determine way. No mitigation required.
- 2: Same as 1, but the device is also aware of SCXTNUM_ELx register
contexts. The TF doesn't use the registers, so there is no
difference with 1.
The field CSV2 was originally introduced in the TRM of the Cortex-A76
before the release of the Armv8.5 architecture. That TRM only mentions
the meaning of values 0 and 1. Because of this, the code only checks if
the field has value 1 to know whether to enable or disable the
mitigations.
This patch makes it aware of value 2 as well. Both values 1 and 2
disable the mitigation, and 0 enables it.
Change-Id: I5af33de25a0197c98173f52c6c8c77b51a51429f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz
committed
on 14 Feb 2019
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stm32mp1: update clock driver
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Remove useless private structure in function prototypes.
Add a reference counter on clocks.
Prepare for future secured/shared/non-secured clocks.
Change-Id: I3dbed81721da5ceff5e10b2c4155b1e340c036ee
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Nicolas LE BAYON <nicolas.le.bayon@st.com>
Yann Gautier
committed
on 14 Feb 2019
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stm32mp1: add timeout detection in reset driver
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This change makes the platform to panic in case of peripheral reset
resource malfunction.
Change-Id: I17eb9cb045b78a4e5142a8c33b744e84992d732a
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Nicolas LE BAYON <nicolas.le.bayon@st.com>
Yann Gautier
committed
on 14 Feb 2019
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stm32mp1: split clkfunc code
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Create a new file stm32mp_clkfunc.c to put functions that could be common
between several platforms.
Change-Id: Ica915c796b162b2345056b33328acc05035a242c
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Yann Gautier
committed
on 14 Feb 2019
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stm32mp1: update I2C and PMIC drivers
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Regulator configuration at boot takes more information from DT.
I2C configuration from DT is done in I2C driver.
I2C driver manages more transfer modes.
The min voltage of buck1 should also be increased to 1.2V,
else the platform does not boot.
Heavily modifies stm32_i2c.c since many functions move inside the source
file to remove redundant declarations.
Change-Id: I0bee5d776cf3ff15e687427cd6abc06ab237d025
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Nicolas LE BAYON <nicolas.le.bayon@st.com>
Yann Gautier
committed
on 14 Feb 2019
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stm32mp1: use new functions to manage timeouts
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Remove the previously use function: get_timer, and use new functions
timeout_init_us and timeout_elapsed.
Change-Id: I4e95b123648bff7ca91e40462a2a3ae24cfe1697
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Nicolas LE BAYON <nicolas.le.bayon@st.com>
Yann Gautier
committed
on 14 Feb 2019
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stm32mp1: make functions and macros more common
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Mainly remove suffix 1 from prefix stm32mp1 in several macros and functions
that can be used in drivers shared by different platforms.
Change-Id: I2295c44f5b1edac7e80a93c0e8dfd671b36e88e7
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Yann Gautier
committed
on 14 Feb 2019
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2019-02-11 |
cpus: Add casts to all definitions in CPU headers
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There are some incorrect casts and some missing casts in the headers.
This patch fixes the ones that were 64-bit or 32-bit wide wrongly and
adds casts where they were missing.
Note that none of the changes of the patch actually changes the values
of the definitions. This patch is just for correctness.
Change-Id: Iad6458021bad521922ce4f91bafff38b116b49eb
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz
committed
on 11 Feb 2019
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cpus: Fix some incorrect definitions in CPU headers
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There are some values that should be 64-bit immediates but that resolve
to 0 because the type of the value is 32-bit wide. This patch casts the
expressions to 64-bit before the shift so that the definition has the
correct value.
The definitions are only used in assembly so far, so the code is not
actually affected by this bug. The assembler treats all values as 64-bit
values, so there are no overflows.
Change-Id: I965e4be631c1d28787c0913661d224c82a6b9155
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz
committed
on 11 Feb 2019
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2019-02-08 |
libc: Move setjmp to libc folder
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Now that setjmp() and longjmp() are compliant with the standard they can
be moved with the other libc files.
Change-Id: Iea3b91c34eb353ace5e171e72f331602d57774d5
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz
committed
on 8 Feb 2019
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