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History for arm-trusted-firmware / docs

2020-07-13	b5cfb04 Browse files » Merge "Add myself and Andre Przywara as code owners for the Arm FPGA platform port" into integration Madhukar Pappireddy authored on 13 Jul 2020 TrustedFirmware Code Review committed on 13 Jul 2020
2020-07-10	f0e2e66 Browse files » Add myself and Andre Przywara as code owners for the Arm FPGA platform port ... Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I6d3949a971fada5a086b788dbe274f8451fcfc0d Javier Almansa Sobrino committed on 10 Jul 2020
2020-07-10	0a977b9 Browse files » plat: marvell: armada: a8k: change CCU LLC SRAM mapping ... The LLC SRAM will be enabled in OP-TEE OS for usage as secure storage. The CCU have to prepare SRAM window, but point to the DRAM-0 target until the SRAM is actually enabled. This patch changes CCU SRAM window target to DRAM-0 Remove dependence between LLC_SRAM and LLC_ENABLE and update the build documentation. The SRAМ base moved to follow the OP-TEE SHMEM area (0x05400000) Change-Id: I85c2434a3d515ec37da5ae8eb729e3280f91c456 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Konstantin Porotchkin authored on 15 Apr 2019 Manish Pandey committed on 10 Jul 2020
2020-07-09	84ef9cd Browse files » make, doc: Add build option to create chain of trust at runtime ... Added a build option 'COT_DESC_IN_DTB' to create chain of trust at runtime using fconf. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I92b257ac4ece8bbf56f05a41d1e4056e2422ab89 Manish V Badarkhe committed on 9 Jul 2020
2020-07-09	b5fb691 Browse files » doc: Update CoT binding to make it more generic ... Updated the CoT binding document to show chain of trust relationship with the help of 'authentication method' and 'authentication data' instead of showing content of certificate and fixed rendering issue while creating html page using this document. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: Ib48279cfe786d149ab69ddc711caa381a50f9e2b Manish V Badarkhe committed on 9 Jul 2020
2020-07-02	1f8ea71 Browse files » Merge "doc: Fix some broken links" into integration Manish Pandey authored on 2 Jul 2020 TrustedFirmware Code Review committed on 2 Jul 2020
2020-07-01	11af40b Browse files » Merge "Workaround for Neoverse N1 erratum 1800710" into integration Lauren Wehrmeister authored on 1 Jul 2020 TrustedFirmware Code Review committed on 1 Jul 2020
2020-07-01	0396bcb Browse files » doc: Fix some broken links ... Fix all external broken links reported by Sphinx linkcheck tool. This does not take care of broken cross-references between internal TF-A documentation files. These will be fixed in a future patch. Change-Id: I2a740a3ec0b688c14aad575a6c2ac71e72ce051e Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Sandrine Bailleux committed on 1 Jul 2020
2020-06-30	c3233c1 Browse files » doc: RAS: fixing broken links ... There were some links in the file "ras.rst" which were broken, this patch fixes all the broken links in this file. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I00cf080e9338af5786239a4843cb4c2e0cc9d99d Manish Pandey committed on 30 Jun 2020
2020-06-26	edd8188 Browse files » Merge changes Ib9c82b85,Ib348e097,I4dc315e4,I58a8ce44,Iebc03361, ... into integration ... * changes: plat: marvell: armada: a8k: add OP-TEE OS MMU tables drivers: marvell: add support for mapping the entire LLC to SRAM plat: marvell: armada: add LLC SRAM CCU setup for AP806/AP807 platforms plat: marvell: armada: reduce memory size reserved for FIP image plat: marvell: armada: platform definitions cleanup plat: marvell: armada: a8k: check CCU window state before loading MSS BL2 drivers: marvell: add CCU driver API for window state checking drivers: marvell: align and extend llc macros plat: marvell: a8k: move address config of cp1/2 to BL2 plat: marvell: armada: re-enable BL32_BASE definition plat: marvell: a8k: extend includes to take advantage of the phy_porting_layer marvell: comphy: initialize common phy selector for AP mode marvell: comphy: update rx_training procedure plat: marvell: armada: configure amb for all CPs plat: marvell: armada: modify PLAT_FAMILY name for 37xx SoCs Manish Pandey authored on 26 Jun 2020 TrustedFirmware Code Review committed on 26 Jun 2020
	d1c54e5 Browse files » doc: Update arg usage for BL2 and BL31 setup functions ... Updated the porting guide for the usage of received arguments in BL2 and BL32 setup functions in case of Arm platform. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: Ia83a5607fed999819d25e49322b3bfb5db9425c0 Manish V Badarkhe authored on 24 Jun 2020 Manish V Badarkhe committed on 26 Jun 2020
	e555787 Browse files » doc: Update BL1 and BL2 boot flow ... Updated the document for BL1 and BL2 boot flow to capture below changes made in FCONF 1. Loading of fw_config and tb_fw_config images by BL1. 2. Population of fw_config and tb_fw_config by BL2. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: Ifea5c61d520ff1de834c279ce1759b53448303ba Manish V Badarkhe authored on 21 Jun 2020 Manish V Badarkhe committed on 26 Jun 2020
	99bcae5 Browse files » Merge changes from topic "fw_config_handoff" into integration ... * changes: doc: Update memory layout for firmware configuration area plat/arm: Increase size of firmware configuration area plat/arm: Load and populate fw_config and tb_fw_config fconf: Handle error from fconf_load_config plat/arm: Update the fw_config load call and populate it's information fconf: Allow fconf to load additional firmware configuration fconf: Clean confused naming between TB_FW and FW_CONFIG tbbr/dualroot: Add fw_config image in chain of trust cert_tool: Update cert_tool for fw_config image support fiptool: Add fw_config in FIP plat/arm: Rentroduce tb_fw_config device tree Sandrine Bailleux authored on 26 Jun 2020 TrustedFirmware Code Review committed on 26 Jun 2020
2020-06-25	0e0521b Browse files » Workaround for Neoverse N1 erratum 1800710 ... Neoverse N1 erratum 1800710 is a Cat B erratum, present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the ECTLR_EL1 system register, which disables allocation of splintered pages in the L2 TLB. This errata is explained in this SDEN: https://static.docs.arm.com/sden885747/f/Arm_Neoverse_N1_MP050_Software_Developer_Errata_Notice_v21.pdf Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Ie5b15c8bc3235e474a06a57c3ec70684361857a6 johpow01 authored on 2 Jun 2020 John Powell committed on 25 Jun 2020
	33fe493 Browse files » Merge "Redirect security incident report to TrustedFirmware.org" into integration Mark Dykes authored on 25 Jun 2020 TrustedFirmware Code Review committed on 25 Jun 2020
	f112d3e Browse files » Merge "doc: Add a binding document for COT descriptors" into integration Mark Dykes authored on 25 Jun 2020 TrustedFirmware Code Review committed on 25 Jun 2020
	62bbfe8 Browse files » Workaround for Cortex A77 erratum 1800714 ... Cortex A77 erratum 1800714 is a Cat B erratum, present in older revisions of the Cortex A77 processor core. The workaround is to set a bit in the ECTLR_EL1 system register, which disables allocation of splintered pages in the L2 TLB. Since this is the first errata workaround implemented for Cortex A77, this patch also adds the required cortex_a77_reset_func in the file lib/cpus/aarch64/cortex_a77.S. This errata is explained in this SDEN: https://static.docs.arm.com/101992/0010/Arm_Cortex_A77_MP074_Software_Developer_Errata_Notice_v10.pdf Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I844de34ee1bd0268f80794e2d9542de2f30fd3ad johpow01 authored on 3 Jun 2020 John Powell committed on 25 Jun 2020
	089fc62 Browse files » doc: Update memory layout for firmware configuration area ... Captured the increase in firmware configuration area from 4KB to 8kB in memory layout document. Updated the documentation to provide details about fw_config separately. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: Ifbec443ced479301be65827b49ff4fe447e9109f Manish V Badarkhe committed on 25 Jun 2020
2020-06-24	1367cc1 Browse files » Redirect security incident report to TrustedFirmware.org ... All projects under the TrustedFirmware.org project now use the same security incident process, therefore update the disclosure/vulnerability reporting information in the TF-A documentation. ------------------------------------------------------------------------ /!\ IMPORTANT /!\ Please note that the email address to send these reports to has changed. Please do not use trusted-firmware-security@arm.com anymore. Similarly, the PGP key provided to encrypt emails to the security email alias has changed as well. Please do not use the former one provided in the TF-A source tree. It is recommended to remove it from your keyring to avoid any mistake. Please use the new key provided on TrustedFirmware.org from now on. ------------------------------------------------------------------------ Change-Id: I14eb61017ab99182f1c45d1e156b96d5764934c1 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Sandrine Bailleux committed on 24 Jun 2020
2020-06-23	ccf5863 Browse files » Merge changes Ifc34f2e9,Iefd58159 into integration ... * changes: Workaround for Cortex A76 erratum 1800710 Workaround for Cortex A76 erratum 1791580 Lauren Wehrmeister authored on 23 Jun 2020 TrustedFirmware Code Review committed on 23 Jun 2020
2020-06-23	ebd34be Browse files » doc: Add a binding document for COT descriptors ... Added a binding document for COT descriptors which is going to be used in order to create COT desciptors at run-time. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: Ic54519b0e16d145cd1609274a00b137a9194e8dd Manish V Badarkhe committed on 23 Jun 2020
2020-06-22	dcbfbcb Browse files » Workaround for Cortex A76 erratum 1800710 ... Cortex A76 erratum 1800710 is a Cat B erratum, present in older revisions of the Cortex A76 processor core. The workaround is to set a bit in the ECTLR_EL1 system register, which disables allocation of splintered pages in the L2 TLB. This errata is explained in this SDEN: https://static.docs.arm.com/sden885749/g/Arm_Cortex_A76_MP052_Software_Developer_Errata_Notice_v20.pdf Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Ifc34f2e9e053dcee6a108cfb7df7ff7f497c9493 johpow01 committed on 22 Jun 2020
2020-06-22	d7b08e6 Browse files » Workaround for Cortex A76 erratum 1791580 ... Cortex A76 erratum 1791580 is a Cat B erratum present in earlier revisions of the Cortex A76. The workaround is to set a bit in the implementation defined CPUACTLR2 register, which forces atomic store operations to write-back memory to be performed in the L1 data cache. This errata is explained in this SDEN: https://static.docs.arm.com/sden885749/g/Arm_Cortex_A76_MP052_Software_Developer_Errata_Notice_v20.pdf Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Iefd58159b3f2e2286138993317b98e57dc361925 johpow01 committed on 22 Jun 2020
2020-06-19	5a40d70 Browse files » drivers: marvell: add support for mapping the entire LLC to SRAM ... Add llc_sram_enable() and llc_sram_disable() APIs to Marvell cache_lls driver. Add LLC_SRAM definition to Marvell common makefile - disabled by the default. Add description of LLC_SRAM flag to the build documentation. Change-Id: Ib348e09752ce1206d29268ef96c9018b781db182 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Konstantin Porotchkin authored on 31 Mar 2019 Marcin Wojtas committed on 19 Jun 2020
2020-06-19	3768fec Browse files » TF-A: Add ARMv8.5 'bti' build option ... This patch adds BRANCH_PROTECTION = 4 'bti' build option which turns on branch target identification mechanism. Change-Id: I32464a6b51726a100519f449a95aea5331f0e82d Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com> Alexei Fedorov committed on 19 Jun 2020
2020-06-17	9935047 Browse files » Merge changes I80316689,I23cac4fb,If911e7de,I169ff358,I4e040cd5, ... into integration ... * changes: ddr: a80x0: add DDR 32-bit ECC mode support ble: ap807: improve PLL configuration sequence ble: ap807: clean-up PLL configuration sequence ddr: a80x0: add DDR 32-bit mode support plat: marvell: mci: perform mci link tuning for all mci interfaces plat: marvell: mci: use more meaningful name for mci link tuning plat: marvell: a8k: remove wrong or unnecessary comments plat: marvell: ap807: enable snoop filter for ap807 plat: marvell: ap807: update configuration space of each CP plat: marvell: ap807: use correct address for MCIx4 register plat: marvell: add support for PLL 2.2GHz mode plat: marvell: armada: make a8k_common.mk and mss_common.mk more generic marvell: armada: add extra level in marvell platform hierarchy Manish Pandey authored on 17 Jun 2020 TrustedFirmware Code Review committed on 17 Jun 2020
2020-06-16	5eeb091 Browse files » Merge changes from topic "tegra194-ras-handling" into integration ... * changes: Tegra194: ras: verbose prints for SErrors Prevent RAS register access from lower ELs Tegra194: SiP: clear RAS corrected error records Tegra194: add RAS exception handling Manish Pandey authored on 16 Jun 2020 TrustedFirmware Code Review committed on 16 Jun 2020
2020-06-15	4f4fc18 Browse files » Add Raghu Krishnamurthy as a TF-A maintainer ... Change-Id: I3726f42f8f3de0cd88bd77a0f9d92a710649d18c Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Sandrine Bailleux committed on 15 Jun 2020
2020-06-12	fbc44bd Browse files » Prevent RAS register access from lower ELs ... This patch adds a build config 'RAS_TRAP_LOWER_EL_ERR_ACCESS' to set SCR_EL3.TERR during CPU boot. This bit enables trapping RAS register accesses from EL1 or EL2 to EL3. RAS_TRAP_LOWER_EL_ERR_ACCESS is disabled by default. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: Ifb0fb0afedea7dd2a29a0b0491a1161ecd241438 Varun Wadekar committed on 12 Jun 2020
2020-06-09	10640d2 Browse files » Merge "GICv3: GIC-600: Detect GIC-600 at runtime" into integration Madhukar Pappireddy authored on 9 Jun 2020 TrustedFirmware Code Review committed on 9 Jun 2020