LuminaSensum/arm-trusted-firmware

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LuminaSensum / arm-trusted-firmware

2019-07-04	93d5e14 Browse files » ti: k3: common: Trap all asynchronous bus errors to EL3 ... These errors are asynchronous and cannot be directly correlated with the exact current running software, so handling them in the same EL is not critical. Handling them in TF-A allows for more platform specific decoding of the implementation defined exception registers Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: Iee7a38c9fc9c698fa0ad42dafa598bcbed6a4fda Andrew F. Davis committed on 4 Jul 2019
2019-07-04	bb2d778 Browse files » Merge changes from topic "lw/n1_errata_fixes" into integration ... * changes: Removing redundant ISB instructions Workaround for Neoverse N1 erratum 1275112 Workaround for Neoverse N1 erratum 1262888 Workaround for Neoverse N1 erratum 1262606 Workaround for Neoverse N1 erratum 1257314 Workaround for Neoverse N1 erratum 1220197 Workaround for Neoverse N1 erratum 1207823 Workaround for Neoverse N1 erratum 1165347 Workaround for Neoverse N1 erratum 1130799 Workaround for Neoverse N1 erratum 1073348 Sandrine Bailleux authored on 4 Jul 2019 TrustedFirmware Code Review committed on 4 Jul 2019
2019-07-02	7d6f751 Browse files » Removing redundant ISB instructions ... Replacing ISB instructions in each Errata workaround with a single ISB instruction before the RET in the reset handler. Change-Id: I08afabc5b98986a6fe81664cd13822b36cab786f Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> lauwal01 committed on 2 Jul 2019
	4d8801f Browse files » Workaround for Neoverse N1 erratum 1275112 ... Neoverse N1 erratum 1275112 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: If7fe55fe92e656fa6aea12327ab297f2e6119833 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> lauwal01 committed on 2 Jul 2019
	11c4837 Browse files » Workaround for Neoverse N1 erratum 1262888 ... Neoverse N1 erratum 1262888 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUECTLR_EL1 system register, which disables the MMU hardware prefetcher. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Ib733d748e32a7ea6a2783f3d5a9c5e13eee01105 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> lauwal01 committed on 2 Jul 2019
	411f495 Browse files » Workaround for Neoverse N1 erratum 1262606 ... Neoverse N1 erratum 1262606 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Idd980e9d5310232d38f0ce272862e1fb0f02ce9a Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> lauwal01 committed on 2 Jul 2019
	335b3c7 Browse files » Workaround for Neoverse N1 erratum 1257314 ... Neoverse N1 erratum 1257314 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR3_EL1 system register, which prevents parallel execution of divide and square root instructions. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I54f0f40ff9043efee40d51e796b92ed85b394cbb Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> lauwal01 committed on 2 Jul 2019
	9eceb02 Browse files » Workaround for Neoverse N1 erratum 1220197 ... Neoverse N1 erratum 1220197 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set two bits in the implementation defined CPUECTLR_EL1 system register, which disables write streaming to the L2. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I9c3373f1b6d67d21ee71b2b80aec5e96826818e8 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> lauwal01 committed on 2 Jul 2019
	ef5fa7d Browse files » Workaround for Neoverse N1 erratum 1207823 ... Neoverse N1 erratum 1207823 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Ia932337821f1ef0d644db3612480462a8d924d21 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> lauwal01 committed on 2 Jul 2019
	2017ab2 Browse files » Workaround for Neoverse N1 erratum 1165347 ... Neoverse N1 erratum 1165347 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set two bits in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I163d0ea00578245c1323d2340314cdc3088c450d Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> lauwal01 committed on 2 Jul 2019
	e34606f Browse files » Workaround for Neoverse N1 erratum 1130799 ... Neoverse N1 erratum 1130799 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I252bc45f9733443ba0503fefe62f50fdea61da6d Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> lauwal01 committed on 2 Jul 2019
	a601afe Browse files » Workaround for Neoverse N1 erratum 1073348 ... Neoverse N1 erratum 1073348 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which disables static prediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I674126c0af6e068eecb379a190bcf7c75dcbca8e Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> lauwal01 committed on 2 Jul 2019
	b01e0ad Browse files » Merge "zynqmp: add support for multi console interface" into integration Sandrine Bailleux authored on 2 Jul 2019 TrustedFirmware Code Review committed on 2 Jul 2019
2019-07-01	0d220b3 Browse files » Merge changes from topic "banned_api_list" into integration ... * changes: Fix the License header template in imx_aipstz.c docs: Add the list of banned/use with caution APIs Soby Mathew authored on 1 Jul 2019 TrustedFirmware Code Review committed on 1 Jul 2019
	2aca35f Browse files » Fix the License header template in imx_aipstz.c ... Signed-off-by: Soby Mathew <soby.mathew@arm.com> Change-Id: I2281b3c1b8a0f2caa751c746b7835f998183e0af Soby Mathew committed on 1 Jul 2019
	140c831 Browse files » docs: Add the list of banned/use with caution APIs ... Credit to sam.ellis@arm.com for the input to create the list. Change-Id: Id70a8eddc5f2490811bebb278482c61950f10cce Signed-off-by: Soby Mathew <soby.mathew@arm.com> Soby Mathew committed on 1 Jul 2019
	55a08b3 Browse files » zynqmp: add support for multi console interface ... This patch addds multi console interface for ZynqMP platform Change-Id: I508a61412df2b71d04bca6a1139c8f32cbd7dccd Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Ambroise Vincent authored on 29 May 2019 Siva Durga Prasad Paladugu committed on 1 Jul 2019
2019-06-28	39c92b6 Browse files » Merge changes from topic "av/console-port" into integration ... * changes: qemu: use new console interface in aarch32 warp7: remove old console from makefile Remove MULTI_CONSOLE_API flag and references to it Console: removed legacy console API Paul Beesley authored on 28 Jun 2019 TrustedFirmware Code Review committed on 28 Jun 2019
	e6ffc25 Browse files » qemu: use new console interface in aarch32 ... Change-Id: Iab788e3e7cb2f83144255c4eb830712fd5cb6240 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com> Ambroise Vincent committed on 28 Jun 2019
	0821731 Browse files » warp7: remove old console from makefile ... Change-Id: I87818b220568cc34838726b32ddf29ee6cf31ed7 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com> Ambroise Vincent committed on 28 Jun 2019
	5b6ebee Browse files » Remove MULTI_CONSOLE_API flag and references to it ... The new API becomes the default one. Change-Id: Ic1d602da3dff4f4ebbcc158b885295c902a24fec Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com> Ambroise Vincent committed on 28 Jun 2019
2019-06-27	e54b4dd Browse files » Merge "Tegra: Fix typo in comment" into integration Paul Beesley authored on 27 Jun 2019 TrustedFirmware Code Review committed on 27 Jun 2019
	8b95f81 Browse files » Merge "Tegra: Extend NS address check error output" into integration Paul Beesley authored on 27 Jun 2019 TrustedFirmware Code Review committed on 27 Jun 2019
	b4c99a9 Browse files » Merge "n1sdp: add code for DDR ECC enablement and BL33 copy to DDR" into integration Paul Beesley authored on 27 Jun 2019 TrustedFirmware Code Review committed on 27 Jun 2019
2019-06-26	de8bc83 Browse files » n1sdp: add code for DDR ECC enablement and BL33 copy to DDR ... N1SDP platform supports RDIMMs with ECC capability. To use the ECC capability, the entire DDR memory space has to be zeroed out before enabling the ECC bits in DMC620. Zeroing out several gigabytes of memory from SCP is quite time consuming so functions are added that zeros out the DDR memory from application processor which is much faster compared to SCP. BL33 binary cannot be copied to DDR memory before enabling ECC so this is also done by TF-A from IOFPGA-DDR3 memory to main DDR4 memory after ECC is enabled. Original PLAT_PHY_ADDR_SPACE_SIZE was limited to 36-bits with which the entire DDR space cannot be accessed as DRAM2 starts in base 0x8080000000. So these macros are redefined for all ARM platforms. Change-Id: If09524fb65b421b7a368b1b9fc52c49f2ddb7846 Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com> Manoj Kumar committed on 26 Jun 2019
	93c7762 Browse files » Merge changes from topic "pull-out-drivers" into integration ... * changes: intel: Add ncore ccu driver intel: Fix watchdog driver structure intel: Fix qspi driver write config intel: Pull out common drivers into platform common Paul Beesley authored on 26 Jun 2019 TrustedFirmware Code Review committed on 26 Jun 2019
	5bf947a Browse files » Merge "rcar_gen3: drivers: pfc: E3: Replace REVERCED with REVERSED" into integration Paul Beesley authored on 26 Jun 2019 TrustedFirmware Code Review committed on 26 Jun 2019
	8a88a22 Browse files » intel: Add ncore ccu driver ... Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I0544315986ee28b23157fdfec3fe5aebae6b860f Hadi Asyrafi committed on 26 Jun 2019
	19e3644 Browse files » intel: Fix watchdog driver structure ... Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I0ffccca7ea83bff35c9f149d7054cd610a59ec01 Hadi Asyrafi committed on 26 Jun 2019
	2a16502 Browse files » intel: Fix qspi driver write config ... Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I5241ed97697b0280b590b47b9173d102d23f305a Hadi Asyrafi committed on 26 Jun 2019