Tegra194: SiP function ID to read SMMU_PER registers ...

This patch introduces SiP function ID, 0xC200FF00, to read SMMU_PER
error records from all supported SMMU blocks.

The register values are passed over to the client via CPU registers
X1 - X3, where

X1 = SMMU_PER[instance #1] | SMMU_PER[instance #0]
X2 = SMMU_PER[instance #3] | SMMU_PER[instance #2]
X3 = SMMU_PER[instance #5] | SMMU_PER[instance #4]

Change-Id: Id56263f558838ad05f6021f8432e618e99e190fc
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra: memctrl: map video memory as uncached ...

Memmap video memory as uncached normal memory by adding flag
'MT_NON_CACHEABLE' in mmap_add_dynamic_region().
This improves the time taken for clearing the non-overlapping video
memory:

test conditions: 32MB memory size, EMC running at 1866MHz, t186
1) without MT_NON_CACHEABLE: 30ms ~ 40ms
<3>[  133.852885]  vpr-heap: update vpr base to 0x00000000c6000000, size=e000000
<3>[  133.860471] _tegra_set_vpr_params[120]: begin
<3>[  133.896481] _tegra_set_vpr_params[123]: end
<3>[  133.908944]  vpr-heap: update vpr base to 0x00000000c6000000, size=c000000
<3>[  133.916397] _tegra_set_vpr_params[120]: begin
<3>[  133.956369] _tegra_set_vpr_params[123]: end
<3>[  133.970394]  vpr-heap: update vpr base to 0x00000000c6000000, size=a000000
<3>[  133.977934] _tegra_set_vpr_params[120]: begin
<3>[  134.013874] _tegra_set_vpr_params[123]: end
<3>[  134.025666]  vpr-heap: update vpr base to 0x00000000c6000000, size=8000000
<3>[  134.033512] _tegra_set_vpr_params[120]: begin
<3>[  134.065996] _tegra_set_vpr_params[123]: end
<3>[  134.075465]  vpr-heap: update vpr base to 0x00000000c6000000, size=6000000
<3>[  134.082923] _tegra_set_vpr_params[120]: begin
<3>[  134.113119] _tegra_set_vpr_params[123]: end
<3>[  134.123448]  vpr-heap: update vpr base to 0x00000000c6000000, size=4000000
<3>[  134.130790] _tegra_set_vpr_params[120]: begin
<3>[  134.162523] _tegra_set_vpr_params[123]: end
<3>[  134.172413]  vpr-heap: update vpr base to 0x00000000c6000000, size=2000000
<3>[  134.179772] _tegra_set_vpr_params[120]: begin
<3>[  134.209142] _tegra_set_vpr_params[123]: end

2) with MT_NON_CACHEABLE: 10ms ~ 18ms
<3>[  102.108702]  vpr-heap: update vpr base to 0x00000000c6000000, size=e000000
<3>[  102.116296] _tegra_set_vpr_params[120]: begin
<3>[  102.134272] _tegra_set_vpr_params[123]: end
<3>[  102.145839]  vpr-heap: update vpr base to 0x00000000c6000000, size=c000000
<3>[  102.153226] _tegra_set_vpr_params[120]: begin
<3>[  102.164201] _tegra_set_vpr_params[123]: end
<3>[  102.172275]  vpr-heap: update vpr base to 0x00000000c6000000, size=a000000
<3>[  102.179638] _tegra_set_vpr_params[120]: begin
<3>[  102.190342] _tegra_set_vpr_params[123]: end
<3>[  102.197524]  vpr-heap: update vpr base to 0x00000000c6000000, size=8000000
<3>[  102.205085] _tegra_set_vpr_params[120]: begin
<3>[  102.216112] _tegra_set_vpr_params[123]: end
<3>[  102.224080]  vpr-heap: update vpr base to 0x00000000c6000000, size=6000000
<3>[  102.231387] _tegra_set_vpr_params[120]: begin
<3>[  102.241775] _tegra_set_vpr_params[123]: end
<3>[  102.248825]  vpr-heap: update vpr base to 0x00000000c6000000, size=4000000
<3>[  102.256069] _tegra_set_vpr_params[120]: begin
<3>[  102.266368] _tegra_set_vpr_params[123]: end
<3>[  102.273400]  vpr-heap: update vpr base to 0x00000000c6000000, size=2000000
<3>[  102.280672] _tegra_set_vpr_params[120]: begin
<3>[  102.290929] _tegra_set_vpr_params[123]: end

Change-Id: I5f604064ce7b8b73ea9ad5860156ae5e2c6cc42a
Signed-off-by: Ken Chang <kenc@nvidia.com>

Tegra: remove support for USE_COHERENT_MEM ...

This patch removes the support for 'USE_COHERENT_MEM' as
Tegra platforms no longer support the feature.

Change-Id: If1c80fc4e5974412572b3bc1fdf9e70b1ee5d4ec
Signed-off-by: Kalyani Chidambaram <kalyanic@nvidia.com>

Tegra: remove circular dependency with common_def.h ...

This patch stops including common_def.h from platform_def.h to
fix a circular depoendency between them.

This means platform_def.h now has to define the linker macros:
* PLATFORM_LINKER_FORMAT
* PLATFORM_LINKER_ARCH

Change-Id: Icd540b1bd32fb37e0e455e9146c8b7f4b314e012
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra: include missing stdbool.h ...

This patch includes the missing stdbool.h header from flowctrl.h
and bpmp_ivc.c files.

Change-Id: If60d19142b1cb8ae663fbdbdf1ffe45cbbdbc1b2
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra: remove support for SEPARATE_CODE_AND_RODATA=0 ...

Tegra platforms will not be supporting SEPARATE_CODE_AND_RODATA=0.

This patch uses the common macros provided by bl_common.h as a result
and adds a check to assert if SEPARATE_CODE_AND_RODATA set is not set
to '1'.

Change-Id: I376ea60c00ad69cb855d89418bdb80623f14800e
Signed-off-by: Kalyani Chidambaram <kalyanic@nvidia.com>

Tegra: assembly version of the 'plat_core_pos_by_mpidr' handler ...

The 'plat_core_pos_by_mpidr' handler gets called very early during boot
and the compiler generated code overwrites the caller's registers.

This patch converts the 'plat_core_pos_by_mpidr' handler into an assembly
function and uses registers x0-x3, to fix this anomaly.

Change-Id: I8d974e007a0bad039defaf77b11a180d899ead3c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra194: reset power state info for CPUs ...

We set deepest power state when offlining a core but that may not be
requested by non-secure sw which controls idle states. It will re-init
this info from non-secure software when the core come online.

This patch resets the power state in the non-secure world context
to allow it to start with a clean slate.

Change-Id: Iafd92cb2a49571aa6eeb9580beaaff4ba55a87dc
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra186: system resume from TZSRAM memory ...

TZSRAM loses power during System suspend, so the entire contents
are copied to TZDRAM before Sysem Suspend entry. The warmboot code
verifies and restores the contents to TZSRAM during System Resume.

This patch removes the code that sets up CPU vector to point to
TZSRAM during System Resume as a result. The trampoline code can
also be completely removed as a result.

Change-Id: I2830eb1db16efef3dfd96c4e3afc41a307588ca1
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra186: disable PROGRAMMABLE_RESET_ADDRESS ...

This patch disables the code to program reset vector for secondary
CPUs to a different entry point, than cold boot. The cold boot entry
point has the ability to differentiate between a cold boot and a warm
boot, that is controlled by the PROGRAMMABLE_RESET_ADDRESS macro. By
reusing the same entry point, we can lock the CPU reset vector during
cold boot.

Change-Id: Iad400841d57c139469e1d29b5d467197e11958c4
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra210: SE: switch SE clock source to CLK_M ...

In SE suspend, switch SE clock source to CLK_M,
to make sure SE clock is on when saving SE context

Change-Id: I57c559825a3ec8e0cc35f7a389afc458a5eed0cb
Signed-off-by: Leo He <leoh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra: increase platform assert logging level to VERBOSE ...

This patch increases the assert logging level for all Tegra platforms
to VERBOSE, to print the actual assertion condition to the console,
improving debuggability.

Change-Id: If3399bde63fa4261522cab984cc9c49cd2073358
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra194: enable dual execution for EL2 and EL3 ...

This patch enables dual execution optimized translations for EL2 and EL3
CPU exception levels.

Change-Id: I28fe98bb05687400f247e94adf44a1f3a85c38b1
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra: aarch64: calculate core position from one place ...

This patch updates 'plat_my_core_pos' handler to call
'plat_core_pos_from_mpidr' instead of implementing the same logic
at two places.

Change-Id: I1e56adaa10dc2fe3440e5507e0e260d8932e6657
Signed-off-by: Kalyani Chidambaram <kalyanic@nvidia.com>

Tegra194: Update t194_nvg.h to v6.7 ...

This patch updates the t194_nvg.h header file received from the CPU
team to v6.7.

Change-Id: I5d25dfc60448e14b7085250946bd002fcb80a774
Signed-off-by: Kalyani Chidambaram <kalyanic@nvidia.com>

Tegra210: Remove "unsupported func ID" error msg ...

The platform sip is reporting a "unsupported function ID" if the
smc function id is not pmc command. When actually the smc function id
could be specific to the tegra sip handler.
This patch removes the error reported.

Change-Id: Ia3c8545d345746c5eea6d75b9e6957ca23ae9ca3
Signed-off-by: Kalyani Chidambaram <kalyanic@nvidia.com>

Tegra210: support for secure physical timer ...

This patch enables on-chip timer1 interrupts for Tegra210 platforms.

Change-Id: Ic7417dc0e69264d7c28aa012fe2322cd30838f3e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra: smmu: export handlers to read/write SMMU registers ...

This patch exports the SMMU register read/write handlers for platforms.

Change-Id: If92f0d3ce820e4997c090b48be7614407bb582da
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra: smmu: remove context save sequence ...

SMMU and MC registers are saved as part of the System Suspend sequence.
The register list includes some NS world SMMU registers that need to be
saved by NS world software instead. All that remains as a result are
the MC registers.

This patch moves code to MC file as a result and renames all the
variables and defines to use the MC prefix instead of SMMU. The
Tegra186 and Tegra194 platform ports are updated to provide the MC
context register list to the parent driver. The memory required for
context save is reduced due to removal of the SMMU registers.

Change-Id: I83a05079039f52f9ce91c938ada6cd6dfd9c843f
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

Tegra: bpmp: fixup TEGRA_CLK_SE values for Tegra186/Tegra194 ...

This patch fixes the SE clock ID being used for Tegra186 and Tegra194
SoCs. Previous assumption, that both SoCs use the same clock ID, was
incorrect.

Change-Id: I1ef0da5547ff2e14151b53968cad9cc78fee63bd
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra194: memctrl: lock some more MC SID security configs ...

The platform code already contains the initial set of MC SID
security configs to be locked during boot. This patch adds some
more configs to the list. Since the reset value of these registers
is already as per expectations, there is no need to change it.

MC SID security configs
- PTCR,
- MIU6R, MIU6W, MIU7R, MIU7W,
- MPCORER, MPCOREW,
- NVDEC1SRD, NVDEC1SRD1, NVDEC1SWR.

Change-Id: Ia9a1f6a6b6d34fb2787298651f7a4792a40b88ab
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

Tegra194: add SE support to generate SHA256 of TZRAM ...

The BL3-1 firmware code is stored in TZSRAM on Tegra194 platforms. This
memory loses power when we enter System Suspend and so its contents are
stored to TZDRAM, before entry. This opens up an attack vector where the
TZDRAM contents might be tampered with when we are in the System Suspend
mode. To mitigate this attack the SE engine calculates the hash of entire
TZSRAM and stores it in PMC scratch, before we copy data to TZDRAM. The
WB0 code will validate the TZDRAM and match the hash with the one in PMC
scratch.

This patch adds driver for the SE engine, with APIs to calculate the hash
and store to PMC scratch registers.

Change-Id: I04cc0eb7f54c69d64b6c34fc2ff62e4cfbdd43b2
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>

Tegra194: store TZDRAM base/size to scratch registers ...

This patch saves the TZDRAM base and size values to secure scratch
registers, for the WB0. The WB0 reads these values and uses them to
verify integrity of the TZDRAM aperture.

Change-Id: I2f5fd11c87804d20e2698de33be977991c9f6f33
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>

Tegra194: fix warnings for extra parentheses ...

armclang displays warnings for extra parentheses, leading to
build failures as warnings are treated as errors.
This patch removes the extra parentheses to fix this issue.

Change-Id: Id2fd6a3086590436eecabc55502f40752a018131
Signed-off-by: Kalyani Chidambaram <kalyanic@nvidia.com>

Tegra186: store TZDRAM base/size to scratch registers ...

This patch saves the TZDRAM base and size values to secure scratch
registers, for the WB0. The WB0 reads these values and uses them to
verify integrity of the TZDRAM aperture.

Change-Id: Ic70914cb958249f06cb58025a24d13734a85e16e
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra186: add SE support to generate SHA256 of TZRAM ...

The BL3-1 firmware code is stored in TZSRAM on Tegra186 platforms. This
memory loses power when we enter System Suspend and so its contents are
stored to TZDRAM, before entry. This opens up an attack vector where the
TZDRAM contents might be tampered with when we are in the System Suspend
mode. To mitigate this attack the SE engine calculates the hash of entire
TZSRAM and stores it in PMC scratch, before we copy data to TZDRAM. The
WB0 code will validate the TZDRAM and match the hash with the one in PMC
scratch.

This patch adds driver for the SE engine, with APIs to calculate the hash
and store SE SHA256 hash-result to PMC scratch registers.

Change-Id: Ib487d5629225d3d99bd35d44f0402d6d3cf27ddf
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>

Tegra186: add support for bpmp_ipc driver ...

This patch enables the bpmp-ipc driver for Tegra186 platforms,
to ask BPMP firmware to toggle SE clock.

Change-Id: Ie63587346c4d9b7e54767dbee17d0139fa2818ae
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>

Tegra210: disable ERRATA_A57_829520 ...

ERRATA_A57_829520 disables "indirect branch prediction" for
EL1 on cpu reset, leading to 15% drop in CPU performance
with coremark benchmarks.

Tegra210 already has a hardware fix for ARM BUG#829520,so
this errata is not needed.

This patch disables the errata to get increased performance
numbers.

Change-Id: I0b42e8badd19a8101f6a55d80eb2d953597d3c20
Signed-off-by: Mithun Maragiri <mmaragiri@nvidia.com>

Tegra194: memctrl: add support for MIU4 and MIU5 ...

This patch adds support for memqual miu 4,5.

The MEMQUAL engine has miu0 to miu7 in which miu6 and
miu7 is hardwired to bypass SMMU. So only miu0 to miu5
support is provided.

Change-Id: Ib350334eec521e65f395f1c3205e2cdaf464ebea
Signed-off-by: Pravin <pt@nvidia.com>

Tegra194: memctrl: remove support to reconfigure MSS ...

As bpmp-fw is running at the same time as ATF, and
the mss client reconfiguration sequence involves performing
a hot flush resets on bpmp, there is a chance that bpmp-fw is
trying to perform accesses while the hot flush is active.

Therefore, the mss client reconfigure has been moved to
System Suspend resume fw and bootloader, and it can be
removed from here.

Change-Id: I34019ad12abea9681f5e180af6bc86f2c4c6fc74
Signed-off-by: Stefan Kristiansson <stefank@nvidia.com>