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2019-07-04	bb2d778 Browse files » Merge changes from topic "lw/n1_errata_fixes" into integration ... * changes: Removing redundant ISB instructions Workaround for Neoverse N1 erratum 1275112 Workaround for Neoverse N1 erratum 1262888 Workaround for Neoverse N1 erratum 1262606 Workaround for Neoverse N1 erratum 1257314 Workaround for Neoverse N1 erratum 1220197 Workaround for Neoverse N1 erratum 1207823 Workaround for Neoverse N1 erratum 1165347 Workaround for Neoverse N1 erratum 1130799 Workaround for Neoverse N1 erratum 1073348 Sandrine Bailleux authored on 4 Jul 2019 TrustedFirmware Code Review committed on 4 Jul 2019
2019-07-02	4d8801f Browse files » Workaround for Neoverse N1 erratum 1275112 ... Neoverse N1 erratum 1275112 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: If7fe55fe92e656fa6aea12327ab297f2e6119833 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> lauwal01 committed on 2 Jul 2019
	11c4837 Browse files » Workaround for Neoverse N1 erratum 1262888 ... Neoverse N1 erratum 1262888 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUECTLR_EL1 system register, which disables the MMU hardware prefetcher. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Ib733d748e32a7ea6a2783f3d5a9c5e13eee01105 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> lauwal01 committed on 2 Jul 2019
	411f495 Browse files » Workaround for Neoverse N1 erratum 1262606 ... Neoverse N1 erratum 1262606 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Idd980e9d5310232d38f0ce272862e1fb0f02ce9a Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> lauwal01 committed on 2 Jul 2019
	335b3c7 Browse files » Workaround for Neoverse N1 erratum 1257314 ... Neoverse N1 erratum 1257314 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR3_EL1 system register, which prevents parallel execution of divide and square root instructions. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I54f0f40ff9043efee40d51e796b92ed85b394cbb Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> lauwal01 committed on 2 Jul 2019
	9eceb02 Browse files » Workaround for Neoverse N1 erratum 1220197 ... Neoverse N1 erratum 1220197 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set two bits in the implementation defined CPUECTLR_EL1 system register, which disables write streaming to the L2. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I9c3373f1b6d67d21ee71b2b80aec5e96826818e8 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> lauwal01 committed on 2 Jul 2019
	ef5fa7d Browse files » Workaround for Neoverse N1 erratum 1207823 ... Neoverse N1 erratum 1207823 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Ia932337821f1ef0d644db3612480462a8d924d21 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> lauwal01 committed on 2 Jul 2019
	2017ab2 Browse files » Workaround for Neoverse N1 erratum 1165347 ... Neoverse N1 erratum 1165347 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set two bits in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I163d0ea00578245c1323d2340314cdc3088c450d Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> lauwal01 committed on 2 Jul 2019
	e34606f Browse files » Workaround for Neoverse N1 erratum 1130799 ... Neoverse N1 erratum 1130799 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I252bc45f9733443ba0503fefe62f50fdea61da6d Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> lauwal01 committed on 2 Jul 2019
	a601afe Browse files » Workaround for Neoverse N1 erratum 1073348 ... Neoverse N1 erratum 1073348 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which disables static prediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I674126c0af6e068eecb379a190bcf7c75dcbca8e Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> lauwal01 committed on 2 Jul 2019
2019-07-01	0d220b3 Browse files » Merge changes from topic "banned_api_list" into integration ... * changes: Fix the License header template in imx_aipstz.c docs: Add the list of banned/use with caution APIs Soby Mathew authored on 1 Jul 2019 TrustedFirmware Code Review committed on 1 Jul 2019
2019-07-01	140c831 Browse files » docs: Add the list of banned/use with caution APIs ... Credit to sam.ellis@arm.com for the input to create the list. Change-Id: Id70a8eddc5f2490811bebb278482c61950f10cce Signed-off-by: Soby Mathew <soby.mathew@arm.com> Soby Mathew committed on 1 Jul 2019
2019-06-25	1b779c8 Browse files » Merge "doc: Fix typo in file interrupt-framework-design.rst" into integration John Tsichritzis authored on 25 Jun 2019 TrustedFirmware Code Review committed on 25 Jun 2019
2019-06-24	2645fce Browse files » Fix links in documentation ... Change-Id: Ifef4d634b4a34d23f42f61df5e326a1cc05d3844 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com> John Tsichritzis committed on 24 Jun 2019
2019-06-22	36a5acf Browse files » doc: Fix typo in file interrupt-framework-design.rst ... Signed-off-by: Peng Donglin <dolinux.peng@gmail.com> Change-Id: I459e7d056735222f6f34e275dbdaf9a389d193fc Peng Donglin committed on 22 Jun 2019
2019-06-20	f56734f Browse files » Merge "doc: Isolate security-related build options" into integration John Tsichritzis authored on 20 Jun 2019 TrustedFirmware Code Review committed on 20 Jun 2019
2019-06-17	196fa6c Browse files » stm32mp1: update doc for U-Boot compilation ... U-Boot should be compiled with stm32mp15_trusted_defconfig which is supported since tag v2019.07-rc1 with commit [1]. The creation of the U-Boot binary with stm32 header is done at U-Boot compilation step, it is no more required to call the extra command. [1] https://git.denx.de/?p=u-boot.git;a=commit;h=015289580f81 Change-Id: Ia875c22184785fc2e02ad07993a649069cd5ce34 Signed-off-by: Yann Gautier <yann.gautier@st.com> Yann Gautier committed on 17 Jun 2019
2019-06-12	2e30237 Browse files » doc: Isolate security-related build options ... Reference security specific build options from the user guide. Change-Id: I0e1efbf47d914cf3c473104175c702ff1a80eb67 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com> Ambroise Vincent committed on 12 Jun 2019
2019-06-11	4143ed8 Browse files » Merge "Update maintainers list" into integration Soby Mathew authored on 11 Jun 2019 TrustedFirmware Code Review committed on 11 Jun 2019
2019-06-10	156dfbc Browse files » Update maintainers list ... Also sort alphabetically the links at the bottom, a couple of them were not sorted. Change-Id: I49a1dbe9e56a36c5fdbace8e4c8b9a5270bc2984 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com> John Tsichritzis committed on 10 Jun 2019
2019-06-10	dc593dd Browse files » Merge "doc: Document E and W build options" into integration Soby Mathew authored on 10 Jun 2019 TrustedFirmware Code Review committed on 10 Jun 2019
2019-06-06	5f5d076 Browse files » Neoverse N1: Introduce workaround for Neoverse N1 erratum 1315703 ... Neoverse N1 erratum 1315703 is a Cat A (rare) erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR2_EL1 system register, which will disable the load-bypass-store feature. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdocpjdoc-466751330-1032/index.html Change-Id: I5c708dbe0efa4daa0bcb6bd9622c5efe19c03af9 Signed-off-by: Andre Przywara <andre.przywara@arm.com> Andre Przywara committed on 6 Jun 2019
2019-06-06	08455b9 Browse files » doc: Document E and W build options ... Change-Id: I0d9dbef7041fcf950bcafcdbbc17c72b4dea9e40 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com> Ambroise Vincent committed on 6 Jun 2019
2019-06-03	49d969b Browse files » Merge "doc: Enable automatic labels for page titles" into integration John Tsichritzis authored on 3 Jun 2019 TrustedFirmware Code Review committed on 3 Jun 2019
2019-06-03	d294409 Browse files » Add information about the mailing list in the docs ... Change-Id: I41ce5323c33a81db13c5cc40de1ac4e221a10cd8 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com> John Tsichritzis committed on 3 Jun 2019
2019-05-31	008c843 Browse files » Removing IRC related info from the documentation ... Change-Id: I5cf8c70a304bf5869cbeb12fa8d39171cff48ebd Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com> John Tsichritzis committed on 31 May 2019
2019-05-30	c4e4df3 Browse files » doc: Enable automatic labels for page titles ... Automatic labelling of document titles is a prerequisite for converting the format of cross-document links. Sphinx will generate (via the enabled extension) a hidden link target for each document title and this can be referred to later, from another page, to link to the target. The plugin options being used require Sphinx >= 2.0.0 so a requirements.txt file has been added. This file is used with the pip package manager for Python so that the correct dependencies are installed. Change-Id: Ic2049db5804aa4a6447608ba4299de958ce0a87d Signed-off-by: Paul Beesley <paul.beesley@arm.com> Paul Beesley committed on 30 May 2019
2019-05-30	f6ad51c Browse files » Further fixes to documentation links ... Change-Id: Ib021c721652d96f6c06ea18741f19a72bba1d00f Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com> John Tsichritzis committed on 30 May 2019
2019-05-29	8416741 Browse files » Merge "Cortex-A55: workarounds for errata 1221012" into integration Paul Beesley authored on 29 May 2019 TrustedFirmware Code Review committed on 29 May 2019
2019-05-28	9af07df Browse files » Cortex-A55: workarounds for errata 1221012 ... The workaround is added to the Cortex-A55 cpu specific file. The workaround is disabled by default and have to be explicitly enabled by the platform integrator. Change-Id: I3e6fd10df6444122a8ee7d08058946ff1cc912f8 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com> Ambroise Vincent committed on 28 May 2019