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2020-10-07	35c7537 Browse files » Workaround for Cortex A77 erratum 1925769 ... Cortex A77 erratum 1925769 is a Cat B erratum, present in older revisions of the Cortex A77 processor core. The workaround is to set bit 8 in the ECTLR_EL1 register, there is a small performance cost (<0.5%) for setting this bit. SDEN can be found here: https://documentation-service.arm.com/static/5f7c35d0d3be967f7be46d33 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I9cf0e0b5dc1e3e32e24279d2632c759cc7bd7ce9 johpow01 authored on 10 Sep 2020 John Powell committed on 7 Oct 2020
2020-10-06	a4fdb89 Browse files » Merge changes from topics "rename-herculesae-a78ae", "rename-zeus-v1" into integration ... * changes: Rename Neoverse Zeus to Neoverse V1 Rename Cortex Hercules AE to Cortex 78 AE Madhukar Pappireddy authored on 6 Oct 2020 TrustedFirmware Code Review committed on 6 Oct 2020
2020-10-05	467937b Browse files » Rename Neoverse Zeus to Neoverse V1 ... Change-Id: Ieb411e2f8092fa82062e619305b680673a8f184f Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com> Jimmy Brisson authored on 30 Sep 2020 Madhukar Pappireddy committed on 5 Oct 2020
2020-10-05	5effe0b Browse files » Rename Cortex Hercules AE to Cortex 78 AE ... Change-Id: Ic0ca51a855660509264ff0d084c068e1421ad09a Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com> Jimmy Brisson authored on 30 Sep 2020 Madhukar Pappireddy committed on 5 Oct 2020
2020-10-03	55ff05f Browse files » Workaround for Cortex A76 erratum 1868343 ... Cortex A76 erratum 1868343 is a Cat B erratum, present in older revisions of the Cortex A76 processor core. The workaround is to set a bit in the CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. This workaround will have a small impact on performance. This workaround is the same as workarounds for errata 1262606 and 1275112, so all 3 have been combined into one function call. SDEN can be found here: https://documentation-service.arm.com/static/5f2bed6d60a93e65927bc8e7 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I7f2f9965f495540a1f84bb7dcc28aff45d6cee5d johpow01 authored on 29 Sep 2020 Alexei Fedorov committed on 3 Oct 2020
2020-09-29	c36aa3c Browse files » Merge "Workaround for Cortex A77 erratum 1508412" into integration Madhukar Pappireddy authored on 29 Sep 2020 TrustedFirmware Code Review committed on 29 Sep 2020
2020-09-29	609115a Browse files » Merge changes I1ecbe5a1,Ib5945c37,Ic6b79648 into integration ... * changes: plat/arm: Add platform support for Morello fdts: add device tree sources for morello platform lib/cpus: add support for Morello Rainier CPUs Manish Pandey authored on 29 Sep 2020 TrustedFirmware Code Review committed on 29 Sep 2020
2020-09-28	2b357c3 Browse files » lib/cpus: add support for Morello Rainier CPUs ... This patch adds CPU support for the Rainier CPU which is derived from Neoverse N1 r4p0 CPU and implements the Morello capability architecture. Change-Id: Ic6b796481da5a66504ecb0648879446edf4c69fb Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com> Manoj Kumar authored on 9 Jul 2020 Chandni Cherukuri committed on 28 Sep 2020
2020-09-25	aa3efe3 Browse files » Workaround for Cortex A77 erratum 1508412 ... Cortex A77 erratum 1508412 is a Cat B Errata present in r0p0 and r1p0. The workaround is a write sequence to several implementation defined registers based on A77 revision. This errata is explained in this SDEN: https://static.docs.arm.com/101992/0010/Arm_Cortex_A77_MP074_Software_Developer_Errata_Notice_v10.pdf Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: I217993cffb3ac57c313db8490e7b8a7bb393379b laurenw-arm committed on 25 Sep 2020
2020-09-25	1994e56 Browse files » arm_fpga: Add support for unknown MPIDs ... This patch allows the system to fallback to a default CPU library in case the MPID does not match with any of the supported ones. This feature can be enabled by setting SUPPORT_UNKNOWN_MPID build option to 1 (enabled by default only on arm_fpga platform). This feature can be very dangerous on a production image and therefore it MUST be disabled for Release images. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I0df7ef2b012d7d60a4fd5de44dea1fbbb46881ba Javier Almansa Sobrino committed on 25 Sep 2020
2020-09-10	61f0ffc Browse files » Workaround for Neoverse N1 erratum 1868343 ... Neoverse N1 erratum 1868343 is a Cat B erratum, present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. This workaround will have a small impact on performance. SDEN can be found here: https://documentation-service.arm.com/static/5f2c130260a93e65927bc92f Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I37da2b3b2da697701b883bff9a1eff2772352844 johpow01 committed on 10 Sep 2020
2020-09-03	7ef3e0b Browse files » Merge "lib: cpu: Check SCU presence in DSU before accessing DSU registers" into integration Manish Pandey authored on 3 Sep 2020 TrustedFirmware Code Review committed on 3 Sep 2020
2020-09-02	942013e Browse files » lib: cpu: Check SCU presence in DSU before accessing DSU registers ... The DSU contains system control registers in the SCU and L3 logic to control the functionality of the cluster. If "DIRECT CONNECT" L3 memory system variant is used, there won't be any L3 cache, snoop filter, and SCU logic present hence no system control register will be present. Hence check SCU presence before accessing DSU register for DSU_936184 errata. Signed-off-by: Pramod Kumar <pramod.kumar@broadcom.com> Change-Id: I1ffa8afb0447ae3bd1032c9dd678d68021fe5a63 Pramod Kumar committed on 2 Sep 2020
2020-08-31	5f90275 Browse files » cpus: denver: skip DCO enable/disable for recent SKUs ... DCO is not supported by the SKUs released after MIDR_PN4. This patch skips enabling or disabling the DCO on these SKUs. Change-Id: Ic31a829de3ae560314d0fb5c5e867689d4ba243b Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Varun Wadekar committed on 31 Aug 2020
	c6d25c0 Browse files » lib: cpus: denver: add MIDR PN9 variant ... This patch introduces support for PN9 variant for some Denver based platforms. Original change by: Hemant Nigam <hnigam@nvidia.com> Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com> Change-Id: I331cd3a083721fd1cd1b03f4a11b32fd306a21f3 Hemant Nigam authored on 17 Dec 2019 Varun Wadekar committed on 31 Aug 2020
	9b624a7 Browse files » cpus: denver: introduce macro to declare cpu_ops ... This patch introduces a macro to declare cpu_op for all Denver SKUs. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: Ibcf88c3256fc5dcaa1be855749ebd2c5c396c977 Varun Wadekar committed on 31 Aug 2020
2020-08-24	601e3ed Browse files » lib: cpus: sanity check pointers before use ... The cpu_ops structure contains a lot of function pointers. It is a good idea to verify that the function pointer is not NULL before executing it. This patch sanity checks each pointer before use to prevent any unforeseen crashes. These checks have been enabled for debug builds only. Change-Id: Ib208331c20e60f0c7c582a20eb3d8cc40fb99d21 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Varun Wadekar authored on 1 Oct 2019 Manish Pandey committed on 24 Aug 2020
2020-08-18	e1c4933 Browse files » lib/cpus: Report AT speculative erratum workaround ... Reported the status (applies, missing) of AT speculative workaround which is applicable for below CPUs. +---------+--------------+ \| Errata \| CPU \| +=========+==============+ \| 1165522 \| Cortex-A76 \| +---------+--------------+ \| 1319367 \| Cortex-A72 \| +---------+--------------+ \| 1319537 \| Cortex-A57 \| +---------+--------------+ \| 1530923 \| Cortex-A55 \| +---------+--------------+ \| 1530924 \| Cortex-A53 \| +---------+--------------+ Also, changes are done to enable common macro 'ERRATA_SPECULATIVE_AT' if AT speculative errata workaround is enabled for any of the above CPUs using 'ERRATA_*' CPU specific build macro. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I3e6a5316a2564071f3920c3ce9ae9a29adbe435b Manish V Badarkhe committed on 18 Aug 2020
2020-08-08	a4a9547 Browse files » lib: cpus: denver: add some MIDR values ... This patch adds support for additional Denver MIDRs to cover all the current SKUs. Change-Id: I85d0ffe9b3cb351f430ca7d7065a2609968a7a28 Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Alex Van Brunt authored on 23 Jul 2019 Varun Wadekar committed on 8 Aug 2020
2020-08-08	5112e60 Browse files » lib: cpus: denver: mark exception vectors as private ... This patch removes the 'workaround_bpflush_runtime_exceptions' exception vector table base address from the globals list as it gets used only by the Denver CPU implementation. Change-Id: I6ef94989f6dc4535d464493cc8621d32795ee1f6 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Varun Wadekar committed on 8 Aug 2020
2020-07-23	f0bbaeb Browse files » Revert workaround for Neoverse N1 erratum 1800710 ... This reverts commit `11af40b`, reversing changes made to `2afcf1d`. This errata workaround did not work as intended so we are reverting this change. In the future, when the corrected workaround is published in an SDEN, we will push a new workaround. This is the patch being reverted: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/4750 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I20aa064c1bac9671939e657bec269d32b9e75a97 johpow01 committed on 23 Jul 2020
2020-06-25	0e0521b Browse files » Workaround for Neoverse N1 erratum 1800710 ... Neoverse N1 erratum 1800710 is a Cat B erratum, present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the ECTLR_EL1 system register, which disables allocation of splintered pages in the L2 TLB. This errata is explained in this SDEN: https://static.docs.arm.com/sden885747/f/Arm_Neoverse_N1_MP050_Software_Developer_Errata_Notice_v21.pdf Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Ie5b15c8bc3235e474a06a57c3ec70684361857a6 johpow01 authored on 2 Jun 2020 John Powell committed on 25 Jun 2020
2020-06-25	62bbfe8 Browse files » Workaround for Cortex A77 erratum 1800714 ... Cortex A77 erratum 1800714 is a Cat B erratum, present in older revisions of the Cortex A77 processor core. The workaround is to set a bit in the ECTLR_EL1 system register, which disables allocation of splintered pages in the L2 TLB. Since this is the first errata workaround implemented for Cortex A77, this patch also adds the required cortex_a77_reset_func in the file lib/cpus/aarch64/cortex_a77.S. This errata is explained in this SDEN: https://static.docs.arm.com/101992/0010/Arm_Cortex_A77_MP074_Software_Developer_Errata_Notice_v10.pdf Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I844de34ee1bd0268f80794e2d9542de2f30fd3ad johpow01 authored on 3 Jun 2020 John Powell committed on 25 Jun 2020
2020-06-22	dcbfbcb Browse files » Workaround for Cortex A76 erratum 1800710 ... Cortex A76 erratum 1800710 is a Cat B erratum, present in older revisions of the Cortex A76 processor core. The workaround is to set a bit in the ECTLR_EL1 system register, which disables allocation of splintered pages in the L2 TLB. This errata is explained in this SDEN: https://static.docs.arm.com/sden885749/g/Arm_Cortex_A76_MP052_Software_Developer_Errata_Notice_v20.pdf Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Ifc34f2e9e053dcee6a108cfb7df7ff7f497c9493 johpow01 committed on 22 Jun 2020
2020-06-22	d7b08e6 Browse files » Workaround for Cortex A76 erratum 1791580 ... Cortex A76 erratum 1791580 is a Cat B erratum present in earlier revisions of the Cortex A76. The workaround is to set a bit in the implementation defined CPUACTLR2 register, which forces atomic store operations to write-back memory to be performed in the L1 data cache. This errata is explained in this SDEN: https://static.docs.arm.com/sden885749/g/Arm_Cortex_A76_MP052_Software_Developer_Errata_Notice_v20.pdf Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Iefd58159b3f2e2286138993317b98e57dc361925 johpow01 committed on 22 Jun 2020
2020-06-09	c5c1af0 Browse files » cpus: denver: disable cycle counter when event counting is prohibited ... The Denver CPUs implement support for PMUv3 for ARMv8.1 and expect the PMCR_EL0 to be saved in non-secure context. This patch disables cycle counter when event counting is prohibited immediately on entering the secure world to avoid leaking useful information about the PMU counters. The context saving code later saves the value of PMCR_EL0 to the non-secure world context. Verified with 'PMU Leakage' test suite. ***************************** Summary ***************************** > Test suite 'PMU Leakage' Passed ================================= Tests Skipped : 2 Tests Passed : 2 Tests Failed : 0 Tests Crashed : 0 Total tests : 4 ================================= Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I3675e2b99b44ed23d86e29a5af1b496e80324875 Varun Wadekar authored on 24 May 2020 Manish Pandey committed on 9 Jun 2020
2020-06-01	3f35709 Browse files » Rename Cortex-Hercules to Cortex-A78 ... Change-Id: I89b90cbdfc8f2aa898b4f3676a4764f060f8e138 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com> Jimmy Brisson committed on 1 Jun 2020
2020-06-01	83c1584 Browse files » Rename Cortex Hercules Files to Cortex A78 ... This should allow git to easily track file moves Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com> Change-Id: I1592cf39a4f94209c560dc6d1a8bc1bfb21d8327 Jimmy Brisson committed on 1 Jun 2020
2020-03-09	e6c0da1 Browse files » cpus: denver: fixup register used to store return address ... The denver_enable_dco and denver_disable_dco use register X3 to store the return address. But X3 gets over-written by other functions, downstream. This patch stores the return address to X18 instead, to fix this anomaly. Change-Id: Ic40bfc1d9abaa7b90348843b9ecd09521bb4ee7b Signed-off-by: Kalyani Chidambaram <kalyanic@nvidia.com> Kalyani Chidambaram authored on 8 Oct 2018 Varun Wadekar committed on 9 Mar 2020
2020-02-21	2f39c55 Browse files » Merge "Add Matterhorn CPU lib" into integration joanna.farley authored on 21 Feb 2020 TrustedFirmware Code Review committed on 21 Feb 2020