LuminaSensum/arm-trusted-firmware

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LuminaSensum / arm-trusted-firmware

2019-07-12	4b5c1f3 Browse files » rcar_gen3: drivers: ddr-a: Update E3 DDR setting ... [IPL/DDR] - Update E3 DDR setting rev.0.12. Signed-off-by: Hiroyuki Nakano <hiroyuki.nakano.cj@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: Ic9fb7ed1cd7588fab169a99c4070a8dfc40038dc Hiroyuki Nakano authored on 15 May 2019 Marek Vasut committed on 12 Jul 2019
2019-07-11	274e871 Browse files » Merge "Aarch64: Fix SCTLR bit definitions" into integration John Tsichritzis authored on 11 Jul 2019 TrustedFirmware Code Review committed on 11 Jul 2019
	ec92cbc Browse files » Merge "plat/intel: Fix SMPLSEL for MMC" into integration John Tsichritzis authored on 11 Jul 2019 TrustedFirmware Code Review committed on 11 Jul 2019
	f15d7e8 Browse files » Merge "driver: synopsys: emmc: Do not change FIFO TH as this breaks some platforms" into integration John Tsichritzis authored on 11 Jul 2019 TrustedFirmware Code Review committed on 11 Jul 2019
	9ce41ec Browse files » driver: synopsys: emmc: Do not change FIFO TH as this breaks some platforms ... Designware MMC DMA FIFO threshold shouldn't be changed as it broke Poplar platform's uboot MMC Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com> Change-Id: I87ec9d5a78e1bf45119cb73797e402b25a914c13 Tien Hock, Loh authored on 3 Jun 2019 John Tsichritzis committed on 11 Jul 2019
	b10fae8 Browse files » Merge "Rename Cortex-Deimos to Cortex-A77" into integration John Tsichritzis authored on 11 Jul 2019 TrustedFirmware Code Review committed on 11 Jul 2019
2019-07-10	c465515 Browse files » Aarch64: Fix SCTLR bit definitions ... This patch removes incorrect SCTLR_V_BIT definition and adds definitions for ARMv8.3-Pauth EnIB, EnDA and EnDB bits. Change-Id: I1384c0a01f56f3d945833464a827036252c75c2e Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com> Alexei Fedorov committed on 10 Jul 2019
2019-07-10	f363deb Browse files » Rename Cortex-Deimos to Cortex-A77 ... Change-Id: I755e4c42242d9a052570fd1132ca3d937acadb13 Signed-off-by: Balint Dobszay <balint.dobszay@arm.com> Balint Dobszay committed on 10 Jul 2019
2019-07-09	0943ea3 Browse files » plat/intel: Fix SMPLSEL for MMC ... MMC sample select needs to be set properly so that DWMMC clock can be driven to 50Mhz Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com> Change-Id: I4a1dde4f6a1e78a36940c57a7a5b162be0bd443a Tien Hock, Loh committed on 9 Jul 2019
	21bde92 Browse files » Merge "plat: imx8m: Add caam module init on imx8m" into integration Sandrine Bailleux authored on 9 Jul 2019 TrustedFirmware Code Review committed on 9 Jul 2019
	a83d8d2 Browse files » Merge changes from topic "jts/reword" into integration ... * changes: docs: removing references to GitHub Change checkpatch.conf after migration to tf.org Sandrine Bailleux authored on 9 Jul 2019 TrustedFirmware Code Review committed on 9 Jul 2019
2019-07-08	2cbeee4 Browse files » Merge "rpi3: Fix compilation error when stack protector is enabled" into integration Sandrine Bailleux authored on 8 Jul 2019 TrustedFirmware Code Review committed on 8 Jul 2019
	f6de960 Browse files » rpi3: Fix compilation error when stack protector is enabled ... Include necessary header file to use ARRAY_SIZE() macro Change-Id: I5b7caccd02c14c598b7944cf4f347606c1e7a8e7 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com> Madhukar Pappireddy committed on 8 Jul 2019
	d012c01 Browse files » docs: removing references to GitHub ... Change-Id: Ibdee91ad337ee362872924d93e82f5b5e47e63d9 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com> John Tsichritzis committed on 8 Jul 2019
	65b5a4b Browse files » Change checkpatch.conf after migration to tf.org ... A specific checkpatch setting was used because of GitHub. This necessity doesn't exist anymore. Change-Id: Ie2225a5cb88654f3b7407e43e0a48fafa9a9165c Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com> John Tsichritzis committed on 8 Jul 2019
2019-07-05	996d379 Browse files » Merge "tools/fiptool: Add Makefile.msvc to build on Windows." into integration Sandrine Bailleux authored on 5 Jul 2019 TrustedFirmware Code Review committed on 5 Jul 2019
	ef4b8d5 Browse files » Merge "uniphier: support console based on multi-console" into integration Sandrine Bailleux authored on 5 Jul 2019 TrustedFirmware Code Review committed on 5 Jul 2019
	ac9f1b5 Browse files » uniphier: support console based on multi-console ... The legacy console is gone. Re-add the console support based on the multi-console framework. I am still keeping the putc, getc, and flush callbacks in uniphier_console.S to use plat/common/aarch64/crash_console_helpers.S The console registration code already relies on that C environment has been set up. So, I just filled the struct console fields with the callback pointers, then called console_register() directly. I also re-implemented the init function in C to improve the readability. Removing the custom crash console implementation has one disadvantage; we cannot use the crash console on very early crashes because crash_console_helpers.S works only after the console is registered. I can live with this limitation. Tested on my boards, and confirmed this worked like before. Change-Id: Ieab9c849853ff6c525c15ea894a85944f257db59 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Masahiro Yamada committed on 5 Jul 2019
	354e263 Browse files » Merge "ti: k3: common: Trap all asynchronous bus errors to EL3" into integration Sandrine Bailleux authored on 5 Jul 2019 TrustedFirmware Code Review committed on 5 Jul 2019
2019-07-04	93d5e14 Browse files » ti: k3: common: Trap all asynchronous bus errors to EL3 ... These errors are asynchronous and cannot be directly correlated with the exact current running software, so handling them in the same EL is not critical. Handling them in TF-A allows for more platform specific decoding of the implementation defined exception registers Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: Iee7a38c9fc9c698fa0ad42dafa598bcbed6a4fda Andrew F. Davis committed on 4 Jul 2019
	2502709 Browse files » plat: imx8m: Add caam module init on imx8m ... CAAM module must be initialized in secure world before it can be used in non-secure world. Change-Id: I042893667ddef99d8b6fc3902847d516d8591996 Signed-off-by: Jacky Bai <ping.bai@nxp.com> Jacky Bai committed on 4 Jul 2019
	bb2d778 Browse files » Merge changes from topic "lw/n1_errata_fixes" into integration ... * changes: Removing redundant ISB instructions Workaround for Neoverse N1 erratum 1275112 Workaround for Neoverse N1 erratum 1262888 Workaround for Neoverse N1 erratum 1262606 Workaround for Neoverse N1 erratum 1257314 Workaround for Neoverse N1 erratum 1220197 Workaround for Neoverse N1 erratum 1207823 Workaround for Neoverse N1 erratum 1165347 Workaround for Neoverse N1 erratum 1130799 Workaround for Neoverse N1 erratum 1073348 Sandrine Bailleux authored on 4 Jul 2019 TrustedFirmware Code Review committed on 4 Jul 2019
2019-07-02	7d6f751 Browse files » Removing redundant ISB instructions ... Replacing ISB instructions in each Errata workaround with a single ISB instruction before the RET in the reset handler. Change-Id: I08afabc5b98986a6fe81664cd13822b36cab786f Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> lauwal01 committed on 2 Jul 2019
	4d8801f Browse files » Workaround for Neoverse N1 erratum 1275112 ... Neoverse N1 erratum 1275112 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: If7fe55fe92e656fa6aea12327ab297f2e6119833 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> lauwal01 committed on 2 Jul 2019
	11c4837 Browse files » Workaround for Neoverse N1 erratum 1262888 ... Neoverse N1 erratum 1262888 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUECTLR_EL1 system register, which disables the MMU hardware prefetcher. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Ib733d748e32a7ea6a2783f3d5a9c5e13eee01105 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> lauwal01 committed on 2 Jul 2019
	411f495 Browse files » Workaround for Neoverse N1 erratum 1262606 ... Neoverse N1 erratum 1262606 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Idd980e9d5310232d38f0ce272862e1fb0f02ce9a Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> lauwal01 committed on 2 Jul 2019
	335b3c7 Browse files » Workaround for Neoverse N1 erratum 1257314 ... Neoverse N1 erratum 1257314 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR3_EL1 system register, which prevents parallel execution of divide and square root instructions. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I54f0f40ff9043efee40d51e796b92ed85b394cbb Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> lauwal01 committed on 2 Jul 2019
	9eceb02 Browse files » Workaround for Neoverse N1 erratum 1220197 ... Neoverse N1 erratum 1220197 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set two bits in the implementation defined CPUECTLR_EL1 system register, which disables write streaming to the L2. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I9c3373f1b6d67d21ee71b2b80aec5e96826818e8 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> lauwal01 committed on 2 Jul 2019
	ef5fa7d Browse files » Workaround for Neoverse N1 erratum 1207823 ... Neoverse N1 erratum 1207823 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Ia932337821f1ef0d644db3612480462a8d924d21 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> lauwal01 committed on 2 Jul 2019
	2017ab2 Browse files » Workaround for Neoverse N1 erratum 1165347 ... Neoverse N1 erratum 1165347 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set two bits in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I163d0ea00578245c1323d2340314cdc3088c450d Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> lauwal01 committed on 2 Jul 2019