2019-03-07 |
doc: Update links within imported wiki content
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This patch covers two changes:
- Links that refer to GitHub are updated to point to the
relevant content on trustedfirmware.org
- Internal links between documents have been updated,
with the required .rst suffix being added or due
to a change in the relative locations of the files.
Change-Id: Ibf87da7d2ece726d1c94a9b33a2bbc3129de7779
Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
Joel Hutton
authored
on 26 Feb 2019
Paul Beesley
committed
on 7 Mar 2019
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doc: Migrate a subset of the GitHub wiki content
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With the TF wiki being migrated from GitHub to trustedfirmware.org,
some documents will be moved into the docs/ directory within the
repository rather than remaining as external content. The
appropriate action has been decided on a per-document basis.
Change-Id: Id0f615f3418369256f30d2e34e354a115389d105
Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
Joel Hutton
authored
on 25 Feb 2019
Paul Beesley
committed
on 7 Mar 2019
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2019-03-06 |
Remove todo from example code
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Keeping that in the docs is a bit untidy
Change-Id: Ia95246208cee48df1536b4317a8c896ab2c84fc2
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
Paul Beesley
committed
on 6 Mar 2019
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2019-03-01 |
Doc: Fix internal links in interrupt framework design guide
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Some of the sections numbers have been incorrect since the document
structure has changed. Using references to sections rather than
hard-coded section numbers fixes the issue while making it more
future-proof to updates.
Change-Id: I80f5ab6a55a0073b1562a02ce2c9ec7d67cddfff
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Sandrine Bailleux
committed
on 1 Mar 2019
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Doc: Fix a formatting glitch
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While converting the interrupt framework design document from Markdown
to reStructuredText format, see commit 6f6257476754 ("Convert
documentation to reStructuredText"), the structure of the document was
changed and one of the titles got lost. Fix that.
Change-Id: Ib3e6c1f9f01f16108fde3b89ceb624bd54049d2f
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Sandrine Bailleux
committed
on 1 Mar 2019
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Merge pull request #1751 from vwadekar/tegra-scatter-file-support
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Tegra scatter file support
Antonio Niño Díaz
authored
on 1 Mar 2019
GitHub
committed
on 1 Mar 2019
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Merge pull request #1849 from loumay-arm/lm/a73_errata
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Cortex-A73: Implement workaround for errata 852427
Antonio Niño Díaz
authored
on 1 Mar 2019
GitHub
committed
on 1 Mar 2019
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Merge pull request #1845 from ambroise-arm/av/errata
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Apply workarounds for errata of Cortex-A53, A55 and A57
Antonio Niño Díaz
authored
on 1 Mar 2019
GitHub
committed
on 1 Mar 2019
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Merge pull request #1848 from antonio-nino-diaz-arm/an/docs
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Minor changes to documentation and comments
Antonio Niño Díaz
authored
on 1 Mar 2019
GitHub
committed
on 1 Mar 2019
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2019-02-28 |
Minor changes to documentation and comments
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Fix some typos and clarify some sentences.
Change-Id: Id276d1ced9a991b4eddc5c47ad9a825e6b29ef74
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz
committed
on 28 Feb 2019
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Cortex-A73: Implement workaround for errata 852427
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In AArch32, execution of 2 instructions with opposite condition code
might lead to either a data corruption or a CPU deadlock. Set the bit
12 of the Diagnostic Register to prevent this.
Change-Id: I22b4f25fe933e2942fd785e411e7c0aa39d5c1f4
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Louis Mayencourt
committed
on 28 Feb 2019
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Merge pull request #1839 from loumay-arm/lm/a7x_errata
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Cortex-A73/75/76 errata workaround
Antonio Niño Díaz
authored
on 28 Feb 2019
GitHub
committed
on 28 Feb 2019
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Cortex-A53: Workarounds for 819472, 824069 and 827319
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The workarounds for these errata are so closely related that it is
better to only have one patch to make it easier to understand.
Change-Id: I0287fa69aefa8b72f884833f6ed0e7775ca834e9
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Ambroise Vincent
committed
on 28 Feb 2019
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Cortex-A57: Implement workaround for erratum 817169
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Change-Id: I25f29a275ecccd7d0c9d33906e6c85967caa767a
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Ambroise Vincent
committed
on 28 Feb 2019
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Cortex-A57: Implement workaround for erratum 814670
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Change-Id: Ice3dcba8c46cea070fd4ca3ffb32aedc840589ad
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Ambroise Vincent
committed
on 28 Feb 2019
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Cortex-A55: Implement workaround for erratum 903758
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Change-Id: I07e69061ba7a918cdfaaa83fa3a42dee910887d7
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Ambroise Vincent
committed
on 28 Feb 2019
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Cortex-A55: Implement workaround for erratum 846532
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Change-Id: Iacb6331c1f6b27340e71279f92f147ebbc71862f
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Ambroise Vincent
committed
on 28 Feb 2019
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Cortex-A55: Implement workaround for erratum 798797
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Change-Id: Ic42b37b8500d5e592af2b9fe130f35a0e2db4d14
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Ambroise Vincent
committed
on 28 Feb 2019
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Cortex-A55: Implement workaround for erratum 778703
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Change-Id: I094e5cb2c44618e7a4116af5fbb6b18078a79951
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Ambroise Vincent
committed
on 28 Feb 2019
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Cortex-A55: Implement workaround for erratum 768277
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Change-Id: Iebd45ef5e39ee7080235fb85414ce5b2e776f90c
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Ambroise Vincent
committed
on 28 Feb 2019
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2019-02-27 |
Tegra: Support for scatterfile for the BL31 image
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This patch provides support for using the scatterfile format as
the linker script with the 'armlink' linker for Tegra platforms.
In order to enable the scatterfile usage the following changes
have been made:
* provide mapping for ld.S symbols in bl_common.h
* include bl_common.h from all the affected files
* update the makefile rules to use the scatterfile and armlink
to compile BL31
* update pubsub.h to add sections to the scatterfile
NOTE: THIS CHANGE HAS BEEN VERIFIED WITH TEGRA PLATFORMS ONLY.
Change-Id: I7bb78b991c97d74a842e5635c74cb0b18e0fce67
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 27 Feb 2019
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Add support for pointer authentication
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The previous commit added the infrastructure to load and save
ARMv8.3-PAuth registers during Non-secure <-> Secure world switches, but
didn't actually enable pointer authentication in the firmware.
This patch adds the functionality needed for platforms to provide
authentication keys for the firmware, and a new option (ENABLE_PAUTH) to
enable pointer authentication in the firmware itself. This option is
disabled by default, and it requires CTX_INCLUDE_PAUTH_REGS to be
enabled.
Change-Id: I35127ec271e1198d43209044de39fa712ef202a5
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz
committed
on 27 Feb 2019
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Add ARMv8.3-PAuth registers to CPU context
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ARMv8.3-PAuth adds functionality that supports address authentication of
the contents of a register before that register is used as the target of
an indirect branch, or as a load.
This feature is supported only in AArch64 state.
This feature is mandatory in ARMv8.3 implementations.
This feature adds several registers to EL1. A new option called
CTX_INCLUDE_PAUTH_REGS has been added to select if the TF needs to save
them during Non-secure <-> Secure world switches. This option must be
enabled if the hardware has the registers or the values will be leaked
during world switches.
To prevent leaks, this patch also disables pointer authentication in the
Secure world if CTX_INCLUDE_PAUTH_REGS is 0. Any attempt to use it will
be trapped in EL3.
Change-Id: I27beba9907b9a86c6df1d0c5bf6180c972830855
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz
committed
on 27 Feb 2019
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Merge pull request #1834 from thloh85-intel/s10_bl31
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plat: intel: Add BL31 support to Intel Stratix10 SoCFPGA platform
Antonio Niño Díaz
authored
on 27 Feb 2019
GitHub
committed
on 27 Feb 2019
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2019-02-26 |
Add workaround for errata 1073348 for Cortex-A76
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Concurrent instruction TLB miss and mispredicted return instruction
might fetch wrong instruction stream. Set bit 6 of CPUACTLR_EL1 to
prevent this.
Change-Id: I2da4f30cd2df3f5e885dd3c4825c557492d1ac58
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Louis Mayencourt
committed
on 26 Feb 2019
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Add workaround for errata 1220197 for Cortex-A76
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Streaming store under specific conditions might cause deadlock or data
corruption. Set bit 25:24 of CPUECTLR_EL1, which disables write
streaming to the L2 to prevent this.
Change-Id: Ib5cabb997b35ada78b27e75787afd610ea606dcf
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Louis Mayencourt
committed
on 26 Feb 2019
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Add workaround for errata 1130799 for Cortex-A76
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TLBI VAAE1 or TLBI VAALE1 targeting a page within hardware page
aggregated address translation data in the L2 TLB might cause
corruption of address translation data. Set bit 59 of CPUACTLR2_EL1 to
prevent this.
Change-Id: I59f3edea54e87d264e0794f5ca2a8c68a636e586
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Louis Mayencourt
committed
on 26 Feb 2019
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Add workaround for errata 790748 for Cortex-A75
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Internal timing conditions might cause the CPU to stop processing
interrupts. Set bit 13 of CPUACTLR_EL1 to prevent this.
Change-Id: Ifdd19dbcdb71bb0d9609cab1315c478aaedb03ba
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Louis Mayencourt
committed
on 26 Feb 2019
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Add workaround for errata 764081 of Cortex-A75
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Implicit Error Synchronization Barrier (IESB) might not be correctly
generated in Cortex-A75 r0p0. To prevent this, IESB are enabled at all
expection levels.
Change-Id: I2a1a568668a31e4f3f38d0fba1d632ad9939e5ad
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Louis Mayencourt
committed
on 26 Feb 2019
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Add workaround for errata 855423 of Cortex-A73
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Broadcast maintainance operations might not be correctly synchronized
between cores. Set bit 7 of S3_0_C15_C0_2 to prevent this.
Change-Id: I67fb62c0b458d44320ebaedafcb8495ff26c814b
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Louis Mayencourt
committed
on 26 Feb 2019
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