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History for arm-trusted-firmware / plat / intel / soc / stratix10

2020-02-28	351d358 Browse files » Merge "intel: Enable EMAC PHY in Intel FPGA platform" into integration Sandrine Bailleux authored on 28 Feb 2020 TrustedFirmware Code Review committed on 28 Feb 2020
2020-02-25	98964f0 Browse files » 16550: Use generic console_t data structure ... Since now the generic console_t structure holds the UART base address as well, let's use that generic location and drop the UART driver specific data structure at all. Change-Id: I5c2fe3b6a667acf80c808cfec4a64059a2c9c25f Signed-off-by: Andre Przywara <andre.przywara@arm.com> Andre Przywara committed on 25 Feb 2020
2020-02-24	d603fd3 Browse files » intel: Enable EMAC PHY in Intel FPGA platform ... This initializes the EMAC PHY in both Stratix 10 and Agilex, without this, EMAC PHY wouldn't work correctly. Change-Id: I7e6b9e88fd9ef472884fcf648e6001fcb7549ae6 Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Tien Hock, Loh authored on 2 Oct 2019 Abdul Halim, Muhammad Hadi Asyrafi committed on 24 Feb 2020
2020-02-12	78fcbd6 Browse files » Merge "intel: Change boot source selection" into integration Sandrine Bailleux authored on 12 Feb 2020 TrustedFirmware Code Review committed on 12 Feb 2020
2020-02-05	e1f97d9 Browse files » intel: Extend SiP service to support mailbox's RSU ... Introduce support for RSU that can be initiated through SMC calls. Added features as below: - RSU status - RSU update - RSU HPS notify - RSU get sub-partition Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I78d5a07688e43da99f03d77dfd45ffb4a78f2e4c Hadi Asyrafi authored on 17 Dec 2019 Abdul Halim, Muhammad Hadi Asyrafi committed on 5 Feb 2020
2020-02-03	77fc469 Browse files » intel: Change boot source selection ... Platform handoff structure no longer includes boot source selection. Hence, those settings can now be configured through socfpga_plat_def.h. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: If7ec6a03bb25156a6670ebf8f77105c370b553f6 Hadi Asyrafi authored on 30 Dec 2019 Abdul Halim, Muhammad Hadi Asyrafi committed on 3 Feb 2020
2020-01-15	f2decc7 Browse files » intel: Add function to check fpga readiness ... Create a function to check for fpga readiness, and move the checking out of bridge enable function. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I3f473ffeffa9ce181a48977560c8bda19c6123c0 Hadi Asyrafi authored on 24 Dec 2019 Abdul Halim, Muhammad Hadi Asyrafi committed on 15 Jan 2020
	9c8f3af Browse files » intel: Add bridge control for FPGA reconfig ... This is to make sure that bridge access in disabled before doing full FPGA reconfiguration and turn re-enable it once the configuration succeed. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I1f42fbf04ac1625048bbdf21b8a0443464ed833d Hadi Asyrafi authored on 23 Dec 2019 Abdul Halim, Muhammad Hadi Asyrafi committed on 15 Jan 2020
	20335ca Browse files » intel: System Manager refactoring ... Refactored system manager driver to be shared across both intel platform Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ic4d056c3d15c3152403dc11641c2452770a6162d Hadi Asyrafi authored on 23 Dec 2019 Abdul Halim, Muhammad Hadi Asyrafi committed on 15 Jan 2020
	391eeee Browse files » intel: Refactor reset manager driver ... Refactor reset manager into intel common platform directory as it can be shared by both Stratix 10 and Agilex. Register address and field is now referred through macros. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Id6d50f2a2f5a6bd8d6746b84602ac17ec7f6c07a Hadi Asyrafi authored on 23 Dec 2019 Abdul Halim, Muhammad Hadi Asyrafi committed on 15 Jan 2020
	3dcb94d Browse files » intel: Enable bridge access in Intel platform ... Add bridge enablement features for each platform. The bridge access will be enabled automatically for FPGA 1st configuration only. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I264757b257a209e1c3c4206660f21c5d67af0d2f Hadi Asyrafi authored on 21 Oct 2019 Abdul Halim, Muhammad Hadi Asyrafi committed on 15 Jan 2020
	222519a Browse files » intel: Modify non secure access function ... Combine both peripheral and bridge non-secure access code into a single callable function Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I38d335ed8d1e9f55d337b63cca121a473897ef70 Hadi Asyrafi authored on 21 Oct 2019 Abdul Halim, Muhammad Hadi Asyrafi committed on 15 Jan 2020
2020-01-14	bc3579b Browse files » Merge "intel: Fix memory calibration" into integration Manish Pandey authored on 14 Jan 2020 TrustedFirmware Code Review committed on 14 Jan 2020
2020-01-08	7a05f06 Browse files » Remove redundant declarations. ... In further patches, we wish to enable -wredundant-decls check as part of warning flags by default. Change-Id: I43410d6dbf40361a503c16d94ccf0f4cf29615b7 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com> Madhukar Pappireddy committed on 8 Jan 2020
2019-12-29	3d9f726 Browse files » intel: Fix memory calibration ... Increase calibration delay to cater for HPS 1st mode and reduce clear emif delay which takes too long Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I1a50a5d8a6518ba085d853cb636efa07326552b4 Hadi Asyrafi committed on 29 Dec 2019
2019-12-16	23f31d3 Browse files » intel: stratix10: Modify BL31 parameter handling ... Add-in support for handling BL31 parameter from non-BL2 image, ie. SPL Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I16118d791399f652b6d1093c10092935a3449c32 Hadi Asyrafi committed on 16 Dec 2019
2019-12-16	2db1e76 Browse files » intel: stratix10: Enable uboot entrypoint support ... This patch will provide an entrypoint for uboot's spl into BL31. BL31 will also handle secondary cpu state during uboot's cold boot Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I661bdb782c2d793d5fc3c7f78dd7ff746e33b7a3 Hadi Asyrafi committed on 16 Dec 2019
2019-12-11	0d1b704 Browse files » intel: s10: Remove unused source code ... remove plat_sip_svc.c and plat_psci.c in stratix 10 platform directory as both has been refactored to common directory for sharing with agilex platform Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I395fed66408f536e8fefd637681e742c63621818 Hadi Asyrafi committed on 11 Dec 2019
2019-11-27	1520b5d Browse files » intel: Refactor common platform code [5/5] ... Removes unused source code for BL2 and BL31 in platform.mk. Clean-up unused header files, syntax fixes, and alphabetical sorting post-refactoring Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ie5ea9b4d3abdb0187cddeb04d2fcfb51fbe5c4dd Hadi Asyrafi committed on 27 Nov 2019
	c76d423 Browse files » intel: Refactor common platform code [4/5] ... Pull out SiP & PSCI service driver into socfpga common directory. Remove deassert_peripheral_reset from cold reset procedure as it is not needed. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I1a0390fca6db4c89919a2a038de2a9d96c3ae4fd Hadi Asyrafi committed on 27 Nov 2019
	d09adcb Browse files » intel: Refactor common platform code [3/5] ... Pull out mailbox driver into common area as they can be shared between intel's socfpga platform Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I4064de1ec668931d77abcb7804f6952b70d33716 Hadi Asyrafi committed on 27 Nov 2019
	e9b5e36 Browse files » intel: Refactor common platform code [2/5] ... Share socfpga private definitions and storage driver between Agilex and Stratix 10 platform. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I6da147f4d2df4a97c505d4bbcffadf63bc3bf4a5 Hadi Asyrafi committed on 27 Nov 2019
	328718f Browse files » intel: Refactor common platform code [1/5] ... Pull out handoff driver to intel/soc/ common directory as they can be shared by both Agilex and Stratix10 platform. Share platform_def header between both Agilex and Stratix10 and store platform specific definitions in socfpga_plat_def.h Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I8eff1afd7ee71704a36a54fad732ede4f557878d Hadi Asyrafi committed on 27 Nov 2019
2019-08-13	fea24b8 Browse files » intel: stratix10: Fix reliance on hard coded clock information ... Extract clock information for UART, MMC & Watchdog from the platform rather than hard code it Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I2582bd34a6da97bd75d5ccba5f93840e65f26b03 Hadi Asyrafi committed on 13 Aug 2019
2019-08-07	5119fa7 Browse files » Merge changes from topic "intel-plat-refactor" into integration ... * changes: intel: Platform common code refactor intel: Platform common code refactor Sandrine Bailleux authored on 7 Aug 2019 TrustedFirmware Code Review committed on 7 Aug 2019
2019-08-07	3f7b149 Browse files » intel: Platform common code refactor ... Pull out common code from aarch64 and include Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I4d0f5e1bb01bcdacbedf8e6c359de594239b645f Hadi Asyrafi authored on 1 Aug 2019 Sandrine Bailleux committed on 7 Aug 2019
2019-08-02	600db4e Browse files » intel: stratix10: Fix BL31 memory mapping ... Previous config blocks ATF runtime service communications with SDM mailbox Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ia857facd0bd0790056df94ed1e016bcf619a161e Hadi Asyrafi committed on 2 Aug 2019
2019-08-01	d882078 Browse files » intel: Platform common code refactor ... Pull out common code from agilex and stratix10 Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Iddc0a9e6eccb30823d7b15615d5ce9c6bedb2abc Hadi Asyrafi committed on 1 Aug 2019
2019-07-16	d0d0f17 Browse files » Merge changes from topic "jc/shift-overflow" into integration ... * changes: Enable -Wshift-overflow=2 to check for undefined shift behavior Update base code to not rely on undefined overflow behaviour Update hisilicon drivers to not rely on undefined overflow behaviour Update synopsys drivers to not rely on undefined overflow behaviour Update imx platform to not rely on undefined overflow behaviour Update mediatek platform to not rely on undefined overflow behaviour Update layerscape platform to not rely on undefined overflow behaviour Update intel platform to not rely on undefined overflow behaviour Update rockchip platform to not rely on undefined overflow behaviour Update renesas platform to not rely on undefined overflow behaviour Update meson platform to not rely on undefined overflow behaviour Update marvell platform to not rely on undefined overflow behaviour Soby Mathew authored on 16 Jul 2019 TrustedFirmware Code Review committed on 16 Jul 2019
2019-07-11	36cfbf3 Browse files » Update intel platform to not rely on undefined overflow behaviour ... This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit. Change-Id: I4c7a315cb18b3bbe623e7a7a998d2dac869638a7 Signed-off-by: Justin Chadwell <justin.chadwell@arm.com> Justin Chadwell committed on 11 Jul 2019