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History for arm-trusted-firmware / plat / intel / soc

2019-09-12	b90f207 Browse files » Invalidate dcache build option for bl2 entry at EL3 ... Some of the platform (ie. Agilex) make use of CCU IPs which will only be initialized during bl2_el3_early_platform_setup. Any operation to the cache beforehand will crash the platform. Hence, this will provide an option to skip the data cache invalidation upon bl2 entry at EL3 Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I2c924ed0589a72d0034714c31be8fe57237d1f06 Hadi Asyrafi authored on 20 Aug 2019 Soby Mathew committed on 12 Sep 2019
2019-09-12	afac968 Browse files » intel: agilex: Fix psci power domain off ... Disable gic cpu interface for powered down cpu. This patch also removes core reset during power off as core reset will be done during power on Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I2ca96d876b6e71e56d24a9a7e184b6d6226b8673 Hadi Asyrafi committed on 12 Sep 2019
2019-09-05	5dbdf8e Browse files » Merge "intel: stratix10: Fix reliance on hard coded clock information" into integration Sandrine Bailleux authored on 5 Sep 2019 TrustedFirmware Code Review committed on 5 Sep 2019
2019-08-28	3441952 Browse files » Merge "intel: agilex: Clear PLL lostlock bypass mode" into integration Paul Beesley authored on 28 Aug 2019 TrustedFirmware Code Review committed on 28 Aug 2019
2019-08-19	24d16a2 Browse files » intel: agilex: HMC driver calculate DDR size ... Driver will calculate DDR size instead of using hardcoded value Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I642cf2180929965ef12bd5ae4393b2f3d0dcddde Hadi Asyrafi committed on 19 Aug 2019
2019-08-18	960a12b Browse files » intel: agilex: Clear PLL lostlock bypass mode ... To provide glitchless clock to downstream logic even if clock toggles Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I728d64d0ba3b4492125bea5b0737fc83180356f1 Hadi Asyrafi committed on 18 Aug 2019
2019-08-15	d1b6013 Browse files » Merge "intel: agilex: Fix memory controller driver" into integration Paul Beesley authored on 15 Aug 2019 TrustedFirmware Code Review committed on 15 Aug 2019
2019-08-14	b266d82 Browse files » intel: agilex: Fix memory controller driver ... Increase calibration delay, fix ddrio control config & nonsecure region limit Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ibca3c247a3ad5104176ca9057d29755599f13c9b Hadi Asyrafi committed on 14 Aug 2019
2019-08-14	4e865bd Browse files » intel: agilex: Fix reliance on hard coded clock information ... Extract clock information for UART, MMC & Watchdog from the clock manager Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I42d3d4ceeaf45788d457472f6ddcd3fe099f0133 Hadi Asyrafi committed on 14 Aug 2019
2019-08-13	fea24b8 Browse files » intel: stratix10: Fix reliance on hard coded clock information ... Extract clock information for UART, MMC & Watchdog from the platform rather than hard code it Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I2582bd34a6da97bd75d5ccba5f93840e65f26b03 Hadi Asyrafi committed on 13 Aug 2019
2019-08-07	5119fa7 Browse files » Merge changes from topic "intel-plat-refactor" into integration ... * changes: intel: Platform common code refactor intel: Platform common code refactor Sandrine Bailleux authored on 7 Aug 2019 TrustedFirmware Code Review committed on 7 Aug 2019
2019-08-07	3f7b149 Browse files » intel: Platform common code refactor ... Pull out common code from aarch64 and include Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I4d0f5e1bb01bcdacbedf8e6c359de594239b645f Hadi Asyrafi authored on 1 Aug 2019 Sandrine Bailleux committed on 7 Aug 2019
2019-08-02	35c28cc Browse files » Merge "intel: stratix10: Fix BL31 memory mapping" into integration Alexei Fedorov authored on 2 Aug 2019 TrustedFirmware Code Review committed on 2 Aug 2019
2019-08-02	600db4e Browse files » intel: stratix10: Fix BL31 memory mapping ... Previous config blocks ATF runtime service communications with SDM mailbox Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ia857facd0bd0790056df94ed1e016bcf619a161e Hadi Asyrafi committed on 2 Aug 2019
2019-08-01	d882078 Browse files » intel: Platform common code refactor ... Pull out common code from agilex and stratix10 Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Iddc0a9e6eccb30823d7b15615d5ce9c6bedb2abc Hadi Asyrafi committed on 1 Aug 2019
2019-07-29	94eef29 Browse files » intel: agilex: Fix BL31 memory mapping ... Previous config blocks ATF runtime service communications with SDM mailbox Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ic97aa381d3ceb96395595ec192132859d626b8d1 Hadi Asyrafi committed on 29 Jul 2019
2019-07-24	3bd24e7 Browse files » intel: agilex: Fix build error ... "result of '1 << 31' requires 33 bits to represent, but 'int' only has 32 bits [-Werror=shift-overflow=]" This is treated as an error since commit 93c690eba8ca ("Enable -Wshift-overflow=2 to check for undefined shift behavior") Change-Id: I141827a6711ab7759bfd6357e4ed9c1176da7c7b Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com> Ambroise Vincent committed on 24 Jul 2019
2019-07-19	b514ee8 Browse files » Merge "intel: Adds support for Agilex platform" into integration Soby Mathew authored on 19 Jul 2019 TrustedFirmware Code Review committed on 19 Jul 2019
2019-07-17	2f11d54 Browse files » intel: Adds support for Agilex platform ... Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ib2ad2068abdf0b204c5cb021ea919581adaca4ef Hadi Asyrafi committed on 17 Jul 2019
2019-07-16	d0d0f17 Browse files » Merge changes from topic "jc/shift-overflow" into integration ... * changes: Enable -Wshift-overflow=2 to check for undefined shift behavior Update base code to not rely on undefined overflow behaviour Update hisilicon drivers to not rely on undefined overflow behaviour Update synopsys drivers to not rely on undefined overflow behaviour Update imx platform to not rely on undefined overflow behaviour Update mediatek platform to not rely on undefined overflow behaviour Update layerscape platform to not rely on undefined overflow behaviour Update intel platform to not rely on undefined overflow behaviour Update rockchip platform to not rely on undefined overflow behaviour Update renesas platform to not rely on undefined overflow behaviour Update meson platform to not rely on undefined overflow behaviour Update marvell platform to not rely on undefined overflow behaviour Soby Mathew authored on 16 Jul 2019 TrustedFirmware Code Review committed on 16 Jul 2019
2019-07-11	36cfbf3 Browse files » Update intel platform to not rely on undefined overflow behaviour ... This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit. Change-Id: I4c7a315cb18b3bbe623e7a7a998d2dac869638a7 Signed-off-by: Justin Chadwell <justin.chadwell@arm.com> Justin Chadwell committed on 11 Jul 2019
2019-07-09	0943ea3 Browse files » plat/intel: Fix SMPLSEL for MMC ... MMC sample select needs to be set properly so that DWMMC clock can be driven to 50Mhz Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com> Change-Id: I4a1dde4f6a1e78a36940c57a7a5b162be0bd443a Tien Hock, Loh committed on 9 Jul 2019
2019-06-28	39c92b6 Browse files » Merge changes from topic "av/console-port" into integration ... * changes: qemu: use new console interface in aarch32 warp7: remove old console from makefile Remove MULTI_CONSOLE_API flag and references to it Console: removed legacy console API Paul Beesley authored on 28 Jun 2019 TrustedFirmware Code Review committed on 28 Jun 2019
2019-06-28	5b6ebee Browse files » Remove MULTI_CONSOLE_API flag and references to it ... The new API becomes the default one. Change-Id: Ic1d602da3dff4f4ebbcc158b885295c902a24fec Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com> Ambroise Vincent committed on 28 Jun 2019
2019-06-26	8a88a22 Browse files » intel: Add ncore ccu driver ... Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I0544315986ee28b23157fdfec3fe5aebae6b860f Hadi Asyrafi committed on 26 Jun 2019
	19e3644 Browse files » intel: Fix watchdog driver structure ... Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I0ffccca7ea83bff35c9f149d7054cd610a59ec01 Hadi Asyrafi committed on 26 Jun 2019
	2a16502 Browse files » intel: Fix qspi driver write config ... Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I5241ed97697b0280b590b47b9173d102d23f305a Hadi Asyrafi committed on 26 Jun 2019
	bf719f6 Browse files » intel: Pull out common drivers into platform common ... Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ib79e2c6fe6e66dec5004701133ad6a5f4c78f2fa Hadi Asyrafi committed on 26 Jun 2019
2019-03-20	10e70f8 Browse files » intel: Enable watchdog timer on Intel S10 platform ... Watchdog driver support & enablement during platform setup Signed-off-by: Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@intel.com> Muhammad Hadi Asyrafi Abdul Halim committed on 20 Mar 2019
2019-03-13	Unverified c61a807 Browse files » Merge pull request #1874 from hadi-asyrafi/qspi_boot ... intel: QSPI boot enablement Soby Mathew authored on 13 Mar 2019 GitHub committed on 13 Mar 2019