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2020-03-09	e6c0da1 Browse files » cpus: denver: fixup register used to store return address ... The denver_enable_dco and denver_disable_dco use register X3 to store the return address. But X3 gets over-written by other functions, downstream. This patch stores the return address to X18 instead, to fix this anomaly. Change-Id: Ic40bfc1d9abaa7b90348843b9ecd09521bb4ee7b Signed-off-by: Kalyani Chidambaram <kalyanic@nvidia.com> Kalyani Chidambaram authored on 8 Oct 2018 Varun Wadekar committed on 9 Mar 2020
2020-02-21	2f39c55 Browse files » Merge "Add Matterhorn CPU lib" into integration joanna.farley authored on 21 Feb 2020 TrustedFirmware Code Review committed on 21 Feb 2020
2020-02-21	e571211 Browse files » Merge "Add CPULib for Klein Core" into integration joanna.farley authored on 21 Feb 2020 TrustedFirmware Code Review committed on 21 Feb 2020
2020-02-20	cd0ea18 Browse files » cpus: higher performance non-cacheable load forwarding ... The CPUACTLR_EL1 register on Cortex-A57 CPUs supports a bit to enable non-cacheable streaming enhancement. Platforms can set this bit only if their memory system meets the requirement that cache line fill requests from the Cortex-A57 processor are atomic. This patch adds support to enable higher performance non-cacheable load forwarding for such platforms. Platforms must enable this support by setting the 'A57_ENABLE_NONCACHEABLE_LOAD_FWD' flag from their makefiles. This flag is disabled by default. Change-Id: Ib27e55dd68d11a50962c0bbc5b89072208b4bac5 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Varun Wadekar committed on 20 Feb 2020
2020-02-18	da3b47e Browse files » Add Matterhorn CPU lib ... Also update copyright statements Change-Id: Iba0305522ac0f2ddc4da99127fd773f340e67300 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com> Jimmy Brisson committed on 18 Feb 2020
2020-02-18	f474472 Browse files » Add CPULib for Klein Core ... Change-Id: I686fd623b8264c85434853a2a26ecd71e9eeac01 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com> Jimmy Brisson committed on 18 Feb 2020
2020-02-04	e693728 Browse files » Coverity: remove unnecessary header file includes ... This patch removes unnecessary header file includes discovered by Coverity HFA option. Change-Id: I2827c37c1c24866c87db0e206e681900545925d4 Signed-off-by: Zelalem <zelalem.aweke@arm.com> Zelalem committed on 4 Feb 2020
2020-01-27	f2d6b4e Browse files » Neovers N1: added support to update presence of External LLC ... CPUECTLR_EL1.EXTLLC bit indicates the presense of internal or external last level cache(LLC) in the system, the reset value is internal LLC. To cater for the platforms(like N1SDP) which has external LLC present introduce a new build option 'NEOVERSE_N1_EXTERNAL_LLC' which can be enabled by platform port. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ibf475fcd6fd44401897a71600f4eafe989921363 Manish Pandey committed on 27 Jan 2020
2020-01-24	5f3ed6a Browse files » Merge "Prevent speculative execution past ERET" into integration Soby Mathew authored on 24 Jan 2020 TrustedFirmware Code Review committed on 24 Jan 2020
2020-01-23	dbafda7 Browse files » Errata workarounds N1 1043202, 1315703 default off ... Setting errata workarounds for N1 1043202 and 1315703 to 0 since they should be turned off by default. Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: I116673a4ddcf64436e90d70133f035a133989ed9 laurenw-arm authored on 22 Jan 2020 Olivier Deprez committed on 23 Jan 2020
2020-01-22	f461fe3 Browse files » Prevent speculative execution past ERET ... Even though ERET always causes a jump to another address, aarch64 CPUs speculatively execute following instructions as if the ERET instruction was not a jump instruction. The speculative execution does not cross privilege-levels (to the jump target as one would expect), but it continues on the kernel privilege level as if the ERET instruction did not change the control flow - thus execution anything that is accidentally linked after the ERET instruction. Later, the results of this speculative execution are always architecturally discarded, however they can leak data using microarchitectural side channels. This speculative execution is very reliable (seems to be unconditional) and it manages to complete even relatively performance-heavy operations (e.g. multiple dependent fetches from uncached memory). This was fixed in Linux, FreeBSD, OpenBSD and Optee OS: https://github.com/torvalds/linux/commit/679db70801da9fda91d26caf13bf5b5ccc74e8e8 https://github.com/freebsd/freebsd/commit/29fb48ace4186a41c409fde52bcf4216e9e50b61 https://github.com/openbsd/src/commit/3a08873ece1cb28ace89fd65e8f3c1375cc98de2 https://github.com/OP-TEE/optee_os/commit/abfd092aa19f9c0251e3d5551e2d68a9ebcfec8a It is demonstrated in a SafeSide example: https://github.com/google/safeside/blob/master/demos/eret_hvc_smc_wrapper.cc https://github.com/google/safeside/blob/master/kernel_modules/kmod_eret_hvc_smc/eret_hvc_smc_module.c Signed-off-by: Anthony Steinhauser <asteinhauser@google.com> Change-Id: Iead39b0b9fb4b8d8b5609daaa8be81497ba63a0f Anthony Steinhauser committed on 22 Jan 2020
2019-12-23	83e9552 Browse files » Workaround for Hercules erratum 1688305 ... Erratum 1688305 is a Cat B erratum present in r0p0, r0p1 versions of Hercules core. The erratum can be avoided by setting bit 1 of the implementation defined register CPUACTLR2_EL1 to 1 to prevent store- release from being dispatched before it is the oldest. Change-Id: I2ac04f5d9423868b6cdd4ceb3d0ffa46e570efed Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com> Madhukar Pappireddy committed on 23 Dec 2019
2019-10-24	22cab65 Browse files » Fix white space errors + remove #if defined ... Fix a few white space errors and remove #if defined in workaround for N1 Errata 1542419. Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: I07ac5a2fd50cd63de53c06e3d0f8262871b62fad laurenw-arm committed on 24 Oct 2019
2019-10-07	25792ce Browse files » Merge "Neoverse N1 Errata Workaround 1542419" into integration Soby Mathew authored on 7 Oct 2019 TrustedFirmware Code Review committed on 7 Oct 2019
2019-10-04	8094262 Browse files » Neoverse N1 Errata Workaround 1542419 ... Coherent I-cache is causing a prefetch violation where when the core executes an instruction that has recently been modified, the core might fetch a stale instruction which violates the ordering of instruction fetches. The workaround includes an instruction sequence to implementation defined registers to trap all EL0 IC IVAU instructions to EL3 and a trap handler to execute a TLB inner-shareable invalidation to an arbitrary address followed by a DSB. Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: Ic3b7cbb11cf2eaf9005523ef5578a372593ae4d6 laurenw-arm authored on 20 Aug 2019 Deepika Bhavnani committed on 4 Oct 2019
2019-10-03	78f02ae Browse files » Introducing support for Cortex-A65AE ... Change-Id: I1ea2bf088f1e001cdbd377cbfb7c6a2866af0422 Signed-off-by: Imre Kis <imre.kis@arm.com> Imre Kis committed on 3 Oct 2019
2019-10-02	6ad216d Browse files » Introducing support for Cortex-A65 ... Change-Id: I645442d52a295706948e2cac88c36c1a3cb0bc47 Signed-off-by: Imre Kis <imre.kis@arm.com> Imre Kis committed on 2 Oct 2019
2019-09-30	a4668c3 Browse files » Cortex_hercules: Add support for Hercules-AE ... Not tested on FVP Model. Change-Id: Iedebc5c1fbc7ea577e94142b7feafa5546f1f4f9 Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com> Artsem Artsemenka committed on 30 Sep 2019
2019-09-11	07f979b Browse files » Zeus: apply the MSR SSBS instruction ... Zeus supports the SSBS mechanism and also the new MSR instruction to immediately apply the mitigation. Hence, the new instruction is utilised in the Zeus-specific reset function. Change-Id: I962747c28afe85a15207a0eba4146f9a115b27e7 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com> John Tsichritzis committed on 11 Sep 2019
2019-08-20	75cfba1 Browse files » Merge "Fix for N1 1043202 Errata Workaround" into integration Alexei Fedorov authored on 20 Aug 2019 TrustedFirmware Code Review committed on 20 Aug 2019
2019-08-19	a33ec1e Browse files » Fix for N1 1043202 Errata Workaround ... ISB instruction was removed from the N1 1043202 Errata Workaround [1], this fix is adding the ISB instruction back in. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: I74eac7f6ad38991c36d423ad6aa44558033ad388 laurenw-arm committed on 19 Aug 2019
2019-08-16	ef430ff Browse files » FVP_Base_AEMv8A platform: Fix cache maintenance operations ... This patch fixes FVP_Base_AEMv8A model hang issue with ARMv8.4+ with cache modelling enabled configuration. Incorrect L1 cache flush operation to PoU, using CLIDR_EL1 LoUIS field, which is required by the architecture to be zero for ARMv8.4-A with ARMv8.4-S2FWB feature is replaced with L1 to L2 and L2 to L3 (if L3 is present) cache flushes. FVP_Base_AEMv8A model can be configured with L3 enabled by setting `cluster0.l3cache-size` and `cluster1.l3cache-size` to non-zero values, and presence of L3 is checked in `aem_generic_core_pwr_dwn` function by reading CLIDR_EL1.Ctype3 field value. Change-Id: If3de3d4eb5ed409e5b4ccdbc2fe6d5a01894a9af Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com> Alexei Fedorov authored on 29 Jul 2019 Paul Beesley committed on 16 Aug 2019
2019-08-01	402b3cf Browse files » Switch AARCH32/AARCH64 to __aarch64__ ... NOTE: AARCH32/AARCH64 macros are now deprecated in favor of __aarch64__. All common C compilers pre-define the same macros to signal which architecture the code is being compiled for: __arm__ for AArch32 (or earlier versions) and __aarch64__ for AArch64. There's no need for TF-A to define its own custom macros for this. In order to unify code with the export headers (which use __aarch64__ to avoid another dependency), let's deprecate the AARCH32 and AARCH64 macros and switch the code base over to the pre-defined standard macro. (Since it is somewhat unintuitive that __arm__ only means AArch32, let's standardize on only using __aarch64__.) Change-Id: Ic77de4b052297d77f38fc95f95f65a8ee70cf200 Signed-off-by: Julius Werner <jwerner@chromium.org> Julius Werner committed on 1 Aug 2019
2019-07-31	3d08461 Browse files » Enable AMU for Cortex-Hercules ... Change-Id: Ie0a94783d0c8e111ae19fd592304e6485f04ca29 Signed-off-by: Balint Dobszay <balint.dobszay@arm.com> Balint Dobszay authored on 15 Jul 2019 Bálint Dobszay committed on 31 Jul 2019
2019-07-16	294f9ef Browse files » Cortex_hercules: Introduce preliminary cpu support ... Change-Id: Iab767e9937f5c6c8150953fcdc3b37e8ee83fa63 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com> Louis Mayencourt committed on 16 Jul 2019
2019-07-10	f363deb Browse files » Rename Cortex-Deimos to Cortex-A77 ... Change-Id: I755e4c42242d9a052570fd1132ca3d937acadb13 Signed-off-by: Balint Dobszay <balint.dobszay@arm.com> Balint Dobszay committed on 10 Jul 2019
2019-07-02	7d6f751 Browse files » Removing redundant ISB instructions ... Replacing ISB instructions in each Errata workaround with a single ISB instruction before the RET in the reset handler. Change-Id: I08afabc5b98986a6fe81664cd13822b36cab786f Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> lauwal01 committed on 2 Jul 2019
	4d8801f Browse files » Workaround for Neoverse N1 erratum 1275112 ... Neoverse N1 erratum 1275112 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: If7fe55fe92e656fa6aea12327ab297f2e6119833 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> lauwal01 committed on 2 Jul 2019
	11c4837 Browse files » Workaround for Neoverse N1 erratum 1262888 ... Neoverse N1 erratum 1262888 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUECTLR_EL1 system register, which disables the MMU hardware prefetcher. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Ib733d748e32a7ea6a2783f3d5a9c5e13eee01105 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> lauwal01 committed on 2 Jul 2019
	411f495 Browse files » Workaround for Neoverse N1 erratum 1262606 ... Neoverse N1 erratum 1262606 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Idd980e9d5310232d38f0ce272862e1fb0f02ce9a Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> lauwal01 committed on 2 Jul 2019