LuminaSensum/arm-trusted-firmware

Fork: 0

LuminaSensum / arm-trusted-firmware

History for arm-trusted-firmware / include / lib / cpus / aarch64

2020-10-09	7d3a7ec Browse files » Merge "Workaround for Cortex A77 erratum 1925769" into integration Lauren Wehrmeister authored on 9 Oct 2020 TrustedFirmware Code Review committed on 9 Oct 2020
2020-10-09	3e0a861 Browse files » lib/cpus: update MIDR value for rainier cpu ... This patch updates the MIDR value for rainier cpu. Change-Id: I99a5d96f757239cf65b2688095c4ec66cd991cf9 Signed-off-by: Jagadeesh Ujja <jagadeesh.ujja@arm.com> Jagadeesh Ujja authored on 7 Oct 2020 jagadeesh.ujja committed on 9 Oct 2020
2020-10-07	35c7537 Browse files » Workaround for Cortex A77 erratum 1925769 ... Cortex A77 erratum 1925769 is a Cat B erratum, present in older revisions of the Cortex A77 processor core. The workaround is to set bit 8 in the ECTLR_EL1 register, there is a small performance cost (<0.5%) for setting this bit. SDEN can be found here: https://documentation-service.arm.com/static/5f7c35d0d3be967f7be46d33 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I9cf0e0b5dc1e3e32e24279d2632c759cc7bd7ce9 johpow01 authored on 10 Sep 2020 John Powell committed on 7 Oct 2020
2020-10-05	467937b Browse files » Rename Neoverse Zeus to Neoverse V1 ... Change-Id: Ieb411e2f8092fa82062e619305b680673a8f184f Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com> Jimmy Brisson authored on 30 Sep 2020 Madhukar Pappireddy committed on 5 Oct 2020
2020-10-05	5effe0b Browse files » Rename Cortex Hercules AE to Cortex 78 AE ... Change-Id: Ic0ca51a855660509264ff0d084c068e1421ad09a Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com> Jimmy Brisson authored on 30 Sep 2020 Madhukar Pappireddy committed on 5 Oct 2020
2020-09-29	c36aa3c Browse files » Merge "Workaround for Cortex A77 erratum 1508412" into integration Madhukar Pappireddy authored on 29 Sep 2020 TrustedFirmware Code Review committed on 29 Sep 2020
2020-09-29	609115a Browse files » Merge changes I1ecbe5a1,Ib5945c37,Ic6b79648 into integration ... * changes: plat/arm: Add platform support for Morello fdts: add device tree sources for morello platform lib/cpus: add support for Morello Rainier CPUs Manish Pandey authored on 29 Sep 2020 TrustedFirmware Code Review committed on 29 Sep 2020
2020-09-28	2b357c3 Browse files » lib/cpus: add support for Morello Rainier CPUs ... This patch adds CPU support for the Rainier CPU which is derived from Neoverse N1 r4p0 CPU and implements the Morello capability architecture. Change-Id: Ic6b796481da5a66504ecb0648879446edf4c69fb Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com> Manoj Kumar authored on 9 Jul 2020 Chandni Cherukuri committed on 28 Sep 2020
2020-09-25	aa3efe3 Browse files » Workaround for Cortex A77 erratum 1508412 ... Cortex A77 erratum 1508412 is a Cat B Errata present in r0p0 and r1p0. The workaround is a write sequence to several implementation defined registers based on A77 revision. This errata is explained in this SDEN: https://static.docs.arm.com/101992/0010/Arm_Cortex_A77_MP074_Software_Developer_Errata_Notice_v10.pdf Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: I217993cffb3ac57c313db8490e7b8a7bb393379b laurenw-arm committed on 25 Sep 2020
2020-09-25	1994e56 Browse files » arm_fpga: Add support for unknown MPIDs ... This patch allows the system to fallback to a default CPU library in case the MPID does not match with any of the supported ones. This feature can be enabled by setting SUPPORT_UNKNOWN_MPID build option to 1 (enabled by default only on arm_fpga platform). This feature can be very dangerous on a production image and therefore it MUST be disabled for Release images. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I0df7ef2b012d7d60a4fd5de44dea1fbbb46881ba Javier Almansa Sobrino committed on 25 Sep 2020
2020-09-03	7ef3e0b Browse files » Merge "lib: cpu: Check SCU presence in DSU before accessing DSU registers" into integration Manish Pandey authored on 3 Sep 2020 TrustedFirmware Code Review committed on 3 Sep 2020
2020-09-02	942013e Browse files » lib: cpu: Check SCU presence in DSU before accessing DSU registers ... The DSU contains system control registers in the SCU and L3 logic to control the functionality of the cluster. If "DIRECT CONNECT" L3 memory system variant is used, there won't be any L3 cache, snoop filter, and SCU logic present hence no system control register will be present. Hence check SCU presence before accessing DSU register for DSU_936184 errata. Signed-off-by: Pramod Kumar <pramod.kumar@broadcom.com> Change-Id: I1ffa8afb0447ae3bd1032c9dd678d68021fe5a63 Pramod Kumar committed on 2 Sep 2020
2020-08-31	c6d25c0 Browse files » lib: cpus: denver: add MIDR PN9 variant ... This patch introduces support for PN9 variant for some Denver based platforms. Original change by: Hemant Nigam <hnigam@nvidia.com> Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com> Change-Id: I331cd3a083721fd1cd1b03f4a11b32fd306a21f3 Hemant Nigam authored on 17 Dec 2019 Varun Wadekar committed on 31 Aug 2020
2020-08-08	a4a9547 Browse files » lib: cpus: denver: add some MIDR values ... This patch adds support for additional Denver MIDRs to cover all the current SKUs. Change-Id: I85d0ffe9b3cb351f430ca7d7065a2609968a7a28 Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Alex Van Brunt authored on 23 Jul 2019 Varun Wadekar committed on 8 Aug 2020
2020-07-23	f0bbaeb Browse files » Revert workaround for Neoverse N1 erratum 1800710 ... This reverts commit `11af40b`, reversing changes made to `2afcf1d`. This errata workaround did not work as intended so we are reverting this change. In the future, when the corrected workaround is published in an SDEN, we will push a new workaround. This is the patch being reverted: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/4750 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I20aa064c1bac9671939e657bec269d32b9e75a97 johpow01 committed on 23 Jul 2020
2020-06-25	0e0521b Browse files » Workaround for Neoverse N1 erratum 1800710 ... Neoverse N1 erratum 1800710 is a Cat B erratum, present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the ECTLR_EL1 system register, which disables allocation of splintered pages in the L2 TLB. This errata is explained in this SDEN: https://static.docs.arm.com/sden885747/f/Arm_Neoverse_N1_MP050_Software_Developer_Errata_Notice_v21.pdf Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Ie5b15c8bc3235e474a06a57c3ec70684361857a6 johpow01 authored on 2 Jun 2020 John Powell committed on 25 Jun 2020
2020-06-25	62bbfe8 Browse files » Workaround for Cortex A77 erratum 1800714 ... Cortex A77 erratum 1800714 is a Cat B erratum, present in older revisions of the Cortex A77 processor core. The workaround is to set a bit in the ECTLR_EL1 system register, which disables allocation of splintered pages in the L2 TLB. Since this is the first errata workaround implemented for Cortex A77, this patch also adds the required cortex_a77_reset_func in the file lib/cpus/aarch64/cortex_a77.S. This errata is explained in this SDEN: https://static.docs.arm.com/101992/0010/Arm_Cortex_A77_MP074_Software_Developer_Errata_Notice_v10.pdf Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I844de34ee1bd0268f80794e2d9542de2f30fd3ad johpow01 authored on 3 Jun 2020 John Powell committed on 25 Jun 2020
2020-06-22	dcbfbcb Browse files » Workaround for Cortex A76 erratum 1800710 ... Cortex A76 erratum 1800710 is a Cat B erratum, present in older revisions of the Cortex A76 processor core. The workaround is to set a bit in the ECTLR_EL1 system register, which disables allocation of splintered pages in the L2 TLB. This errata is explained in this SDEN: https://static.docs.arm.com/sden885749/g/Arm_Cortex_A76_MP052_Software_Developer_Errata_Notice_v20.pdf Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Ifc34f2e9e053dcee6a108cfb7df7ff7f497c9493 johpow01 committed on 22 Jun 2020
2020-06-22	d7b08e6 Browse files » Workaround for Cortex A76 erratum 1791580 ... Cortex A76 erratum 1791580 is a Cat B erratum present in earlier revisions of the Cortex A76. The workaround is to set a bit in the implementation defined CPUACTLR2 register, which forces atomic store operations to write-back memory to be performed in the L1 data cache. This errata is explained in this SDEN: https://static.docs.arm.com/sden885749/g/Arm_Cortex_A76_MP052_Software_Developer_Errata_Notice_v20.pdf Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Iefd58159b3f2e2286138993317b98e57dc361925 johpow01 committed on 22 Jun 2020
2020-06-01	3f35709 Browse files » Rename Cortex-Hercules to Cortex-A78 ... Change-Id: I89b90cbdfc8f2aa898b4f3676a4764f060f8e138 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com> Jimmy Brisson committed on 1 Jun 2020
2020-06-01	83c1584 Browse files » Rename Cortex Hercules Files to Cortex A78 ... This should allow git to easily track file moves Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com> Change-Id: I1592cf39a4f94209c560dc6d1a8bc1bfb21d8327 Jimmy Brisson committed on 1 Jun 2020
2020-04-02	9cefb4b Browse files » Pass more -D options to BL_CPPFLAGS instead of BL_CFLAGS ... Commit d5e97a1d2c79 ("Build: define IMAGE_AT_EL1 or IMAGE_AT_EL3 globally for C files") does not have commit 848a7e8ce1d9 ("Build: introduce per-BL CPPFLAGS and ASFLAGS") as an ancestor because they were pulled almost at the same time. This is a follow-up conversion to be consistent with commit 11a3c5ee7325 ("plat: pass -D option to BL_CPPFLAGS instead of BL_CFLAGS"). With this change, the command line option, IMAGE_AT_EL3, will be passed to .S files as well. I remove the definition in include/lib/cpus/aarch64/cpu_macros.S Otherwise, the following error would happen. include/lib/cpus/aarch64/cpu_macros.S:29:0: error: "IMAGE_AT_EL3" redefined [-Werror] Change-Id: I943c8f22356483c2ae3c57b515c69243a8fa6889 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Masahiro Yamada committed on 2 Apr 2020
2020-03-18	d55b8f6 Browse files » Tegra194: enable dual execution for EL2 and EL3 ... This patch enables dual execution optimized translations for EL2 and EL3 CPU exception levels. Change-Id: I28fe98bb05687400f247e94adf44a1f3a85c38b1 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Kalyani Chidambaram authored on 12 Sep 2018 Varun Wadekar committed on 18 Mar 2020
2020-02-21	2f39c55 Browse files » Merge "Add Matterhorn CPU lib" into integration joanna.farley authored on 21 Feb 2020 TrustedFirmware Code Review committed on 21 Feb 2020
2020-02-21	e571211 Browse files » Merge "Add CPULib for Klein Core" into integration joanna.farley authored on 21 Feb 2020 TrustedFirmware Code Review committed on 21 Feb 2020
2020-02-20	cd0ea18 Browse files » cpus: higher performance non-cacheable load forwarding ... The CPUACTLR_EL1 register on Cortex-A57 CPUs supports a bit to enable non-cacheable streaming enhancement. Platforms can set this bit only if their memory system meets the requirement that cache line fill requests from the Cortex-A57 processor are atomic. This patch adds support to enable higher performance non-cacheable load forwarding for such platforms. Platforms must enable this support by setting the 'A57_ENABLE_NONCACHEABLE_LOAD_FWD' flag from their makefiles. This flag is disabled by default. Change-Id: Ib27e55dd68d11a50962c0bbc5b89072208b4bac5 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Varun Wadekar committed on 20 Feb 2020
2020-02-18	da3b47e Browse files » Add Matterhorn CPU lib ... Also update copyright statements Change-Id: Iba0305522ac0f2ddc4da99127fd773f340e67300 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com> Jimmy Brisson committed on 18 Feb 2020
2020-02-18	f474472 Browse files » Add CPULib for Klein Core ... Change-Id: I686fd623b8264c85434853a2a26ecd71e9eeac01 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com> Jimmy Brisson committed on 18 Feb 2020
2020-01-27	f2d6b4e Browse files » Neovers N1: added support to update presence of External LLC ... CPUECTLR_EL1.EXTLLC bit indicates the presense of internal or external last level cache(LLC) in the system, the reset value is internal LLC. To cater for the platforms(like N1SDP) which has external LLC present introduce a new build option 'NEOVERSE_N1_EXTERNAL_LLC' which can be enabled by platform port. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ibf475fcd6fd44401897a71600f4eafe989921363 Manish Pandey committed on 27 Jan 2020
2019-12-30	0348ee4 Browse files » Merge "Workaround for Hercules erratum 1688305" into integration Manish Pandey authored on 30 Dec 2019 TrustedFirmware Code Review committed on 30 Dec 2019