Merge branch 'for-next/at91'

Merge branch 'for-next/arm'

Release v2019.10.0 ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: add basic sama5d2-som1-ek1 support ...

The ATSAMA5D27-SOM1-EK1 is Microchip's evaluation kit for the SAMA5D2
System in Packages (SiPs). The ATSAMA5D27C-D1G-CU SIP embeds 128 MB
of DDR2 DRAM and the SoM has a PMIC, QSPI flash and a 100Mbps PHY.

barebox already supports the sama5d2 clocks, GPIO/Pinctrl, QSPI
controller and Ethernet MAC. Most notable omission is the sama5d2
variant of the SDHCI, which differs from the MCI used by previous AT91
boards, but we kernel boot over the network works, so lets add the board
now and have the SDHCI follow later.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: add basic sama5d2 support ...

Add hardware description, chip identification and clock changes to
support the sama5d2 SoC.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: microchip-ksz9477-evb: add debug_ll UART ...

The EVB has the dbgu TX on PB31. Pinmux and set up the UART on it when
DEBUG_LL is enabled, so early barebox boot messages can be printed.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: import lowlevel dbgu UART init code from at91bootstrap ...

For use in PBL, import dbgu init code from:
https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/driver/at91_usart.c

The brgr calculation at the beginning is a untangled version
of the BAUDRATE macro from the usart.h header:

	#define BAUDRATE(mck, baud) \
		(((((mck) * 10) / ((baud) * 16)) % 10) >= 5) ? \
		(mck / (baud * 16) + 1) : ((mck) / (baud * 16))

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: import lowlevel clock initialization from at91bootstrap ...

For use by future at91 first stage bootloaders, this commit imports
https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/driver/pmc.c

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

LICENSES: add BSD-1-Clause license ...

Incoming sama5d3 bootstrap code has been ported from the at91bootstrap
project and is licensed under a 1-Clause BSD License. To remove
boilerplate legal text there, place the license at a fixed location
and only note SPDX-License-Identifier and Copyright in the source files.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: use compressed DTB for AT91_MULTI_BOARDS ...

To offset the size increase by using multi-image have the DTBs be
compressed. This reduces e.g. the microchip_ksz9477_evb_defconfig
by about 22K from 244K to 222K.
This will also come in handy when implementing first stage support
later on.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: build for all SoCs when AT91_MULTI_BOARDS is selected ...

With the addition of 15afd9d25 ("ARM: at91: Add initial support for the
EVB-KSZ9477 eval board"), we now have two multi-image capable boards
supported, but users still have to choose a specific SoC, so they can't
be selected at the same time.

Fix this, by restricting the menu to the non-multi-image configurations,
i.e. CONFIG_ARCH_* symbols become specific to non-multi-image.

The multi-image configurations on the other hand directly select the
CONFIG_SOC_* symbol they require. Existing CONFIG_ARCH_* usage is
adjusted to align with the new usage.

Eventually, we would want to have a at91_multi_defconfig along with
this, but for now leave existing configs as is.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: don't define ARCH_BAREBOX_MAX_BARE_INIT_SIZE for multi-image ...

Since ed04a7c3 ("pbl multiimage: Allow to check image sizes"), we can
now check sizes per entry point, so no need to a Kconfig symbol that
applies to all boards for that. Thus drop the Kconfig symbol for
multi-image, so per-entry-point max image sizes can follow in future.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

usb: gadget: at91_udc: don't depend on !ARCH_SAMA5D4 ...

The negative depends rules out using UDC for some targets of a
multi-image barebox while still supporting SAMA5D4.
We don't (yet) have such a configuration, but seeing as there is little
to gain by restricting the selection, drop it.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: delete no-longer needed #ifdef guards ...

c16bcbc644 ("ARM: at91: remove unused defines") removed conflicting
definitions from the headers, so we can include the headers
and code that uses them unconditionally now.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: at91sam9x5ek: squelch new dtc warning ...

Since v1.5.0, dtc has been applying a heuristic to detect spi busses. It
erroneously thinks the spi node in at91sam9x5ek.dts defines a spi bus:

  ./arch/arm/dts/at91sam9x5ek.dts:25.9-29.7: Warning (spi_bus_bridge):
  	/ahb/apb/pinctrl@fffff400/spi: incorrect #address-cells for SPI bus
  ./arch/arm/dts/at91sam9x5ek.dts:25.9-29.7: Warning (spi_bus_bridge):
  	/ahb/apb/pinctrl@fffff400/spi: incorrect #size-cells for SPI bus
  ./arch/arm/dts/at91sam9x5ek.dtb: Warning (spi_bus_reg):
  	Failed prerequisite 'spi_bus_bridge'

Avoid this by renaming the node. While at it move the node to top-level
to reduce indentation.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: mmu: use client domain permissions to support ARMv7 eXecute Never ...

The ARM Architecture Reference Manual notes[1]:
> When using the Short-descriptor translation table format, the XN
> attribute is not checked for domains marked as Manager.
> Therefore, the system must not include read-sensitive memory in
> domains marked as Manager, because the XN bit does not prevent
> speculative fetches from a Manager domain.

To avoid speculative access to read-sensitive memory-mapped peripherals
on ARMv7, let's use client domain permissions for all memory, so the XN
bit (and also R/W bits) can function.
This aligns us with what Linux is doing on ARMv7.

This fixes cache corruption instances that had been observed on the
i.MX6UL(L) when the instruction prefetcher speculates into memory following
the end of a 512M SDRAM[2].

While this is not necessary to avoid speculative accesses on < ARMv7,
we could probably have everything there in client domain as well, but
due to lack of test coverage, we'll restrict the change to ARMv7.

[1]: B3.7.2 - Execute-never restrictions on instruction fetching
[2]: "Cache Corruption on MX6UL(L)": https://community.nxp.com/thread/511925

Fixes: 0198567c4 ("ARM: mmu: mark uncached regions as eXecute never on v7")
Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: mmu: set R/W bits in ARMv7 translation table ...

With barebox using the manager permissions for domain 0 that's used for
all page table entries and directories, we never had the need so far to
explicitly set R/W bits. We did so anyway for sections in the early MMU
code, but later on in the normal MMU setup, we didn't do so consistently.

In preparation for switching to DOMAIN_CLIENT for ARMv7, configure R/W
everywhere in normal MMU code as well.

Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: cache-armv7: remove duplicate domain initialization ...

We already call set_domain each time we do __mmu_cache_on. Writing the
DACR in the armv7 __mmu_cache_on is thus superfluous. Drop it.

This changes existing behavior, whereas all 16 memory domains had the same
access permissions set (manager) before, now only the first domain has.
This is ok, as we only ever use domain 0 in barebox and on non-armv7,
we don't bother with the other ones at all.

Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: cache-armv7: remove superfluous instruction ...

There are two tst r11, #0xf with nothing in between them that changes
r11. This a left over from the kernel code that checks for VMSA twice,
once to check if the page table should be setup and once to more to
flush the TLB. We do the setup in the caller already, so the tst serves
no useful purpose. Delete one.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: mmu: remove no longer accurate comment ...

This comment refers to the state of things prior to e3e54c644
("ARM: mmu: Implement on-demand PTE allocation"). Since then, we no
longer generate 2nd level page tables directly below. Remove it
to avoid confusion.

Cc: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: use system.h's get_cr() for cpuinfo ...

Instead of open-coding the get_cr(), use the already available helper
in <asm/system.h> same as we do for 64-bit ARMv8.
The only difference is that the "memory" clobber is replaced by "cc".
This is ok as we don't expect get_cr() to affect memory and because
we do it elsewhere in barebox without a "memory" clobber already.

While at it, move it out the #if/#else clause as the helper changes
behavior depending on the same CONFIG option anyway.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: stm32mp: add bootm handler for images ...

STM32 images are preceded by a fixed-size 256 byte header, which is
interpreted by the TF-A first stage bootloader and isn't executable
as ARM code.

To maintain the ability to network boot them, add a bootm handler that
skips the header.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

pinctrl: add gpio and pinctrl driver for sama5d2 PIO4 ...

The sama5d2 features a GPIO and pin controller different than the one
we support in barebox. The device tree bindings are different as well,
so it makes sense to have a separate driver for it.

Add the pin control and GPIO driver as well as some helpers usable
from PBL, should we want to do pinmuxing that early.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: provide at91_mux_pio3_pin for use in first stage ...

Low level init code may wish the ability to configure pins, e.g. for low
level debug UART. The pinctrl-at91 driver already exports an
at91_mux_pio3_pin function, but that one is only usable after driver
probe. Instead, provide an at91_mux_pio3_pin function, which can be used
at all times.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

fix compile error when set CONFIG_CONSOLE_SIMPLE=y ...

Signed-off-by: DU HUANPENG <u74147@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Documentation: zii-vf610-dev: Fix bogus DDR configuration values ...

There's a clear mismatch between actual TCL code and comment right
next to it. Comments are definetly right, so fix the TCL code.

Fixes: 02738f4b59 ("Documentation: zii-vf610-dev: Reconcile DDR setup with DCD")
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: aarch64: add image markers to linker script ...

The __image_start and __image_end marker are used by barebox to
calculate the size of the barebox binary inside the RAM. Without the
definitions barebox calculates its own size to zero, which works until a
certain size is exceeded, than the PBL will place the binary lower into
memory than the calculation inside barebox.
Fix this by adding the appropriate image markers to the linker script.

Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

input: specialkeys: remove unused printk argument ...

Two pr_info calls have no format specifiers, but are still passed an
argument. Remove the unused arguments.

Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mci: imx-esdhc-pbl: Fix watermark level value for i.MX ...

Layerscape and i.MX have different semantics of Watermark Level
Register. Whereas the former uses "0" to signify maximum allowed
value, the latter does not.

According to the RM (i.MX8MQ, i.MX6):

"...The read burst length must be less than or equal to the read
watermark level.."

Setting Watermark Level Register to zero violates that limitation. It
appears that, on i.MX8MQ, not following that rule causes certain
configs + toolchains to result in non-bootable image. Specifically,
polling for CICHB, CIDHB and DLA to clear in esdhc_send_cmd() times
out. There doesn't appear to be any clear relationship as to what kind
of image will have the problem, but the following combinations failed
to boot on ZII i.MX8MQ Zest board:

  - gcc version 9.2.1 20190827 (Red Hat Cross 9.2.1-1) (GCC) +
    imx_v8_defconfig + CONFIG_DEBUG_LL and CONFIG_PBL_CONSOLE

  - gcc version 5.5.0 (Timesys 20190405) (custom toolchain) +
    imx_v8_defconfig

Setting WML's *_BRST_LE to 16 and *_WML to 128 on i.MX resolves the
issue (same setting that's selected by writing 0 on Layerscape).

Fixes: 48562aeaa8 ("esdhc-xload: check for PRSSTAT_BREN only after each block")
Cc: Chris Healy <cphealy@gmail.com>
Cc: Ruslan Sushko <ruslan.sushko@zii.aero>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Tested-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: aarch64: Re-implement most of barebox_arm_entry() in assembly ...

GCC9 now produces the following warning:

common.h:51:2: warning: listing the stack pointer register ‘sp’ in a clobber list is deprecated [-Wdeprecated]
   51 |  __asm__ __volatile__("mov sp, %0"
      |  ^~~~~~~
common.h:51:2: note: the value of the stack pointer after  an ‘asm’ statement must be the same as it was before the statement

Stack pointer was added to clobber list in commit f9fc8254b2 ("ARM:
Mark SP as being clobbered in arm_setup_stack()") to prevent GCC from
generating code that would corrupt 'boarddata' pointer by trying to
restore it from invalid stack frame.

Interestingly enough, seemingly unrelated change in commit
64d95896cf ("ARM: aarch64: compile with general-regs-only") changed
generated code such that adding SP to clobber list became no longer
necessary.

While the above can probably be a fix by itself, it seems a better and
more future proof approach would be to address the problem at its root
and re-implement offending startup sequence in assembly.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>