ARM: i.MX53 vincell: Fix lowlevel startup ...

This is a i.MX53 board, not i.MX51.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: pbl: Always call pbl make ...

We always must decend into the pbl build. Otherwise it doesn't get
rebuilt if only sourcefiles from the pbl are changed.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Release v2013.05.1 ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

make: Add barebox_default_env.* to targets ...

Otherwise it gets rebuilt everytime.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: pbl: fix make dependencies ...

The pbl used 'zbarebox.bin' as target instead of the real file. This
lead to strange effects that the images depending on zbarebox.bin were
only built every second time. This uses the full path as target.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

pbl: Fix typo in make causing pbl files to be rebuilt ...

We had pbl_cc__o_c instead of pbl_cc_o_c. This caused all pbl object
files to be rebuilt everytime due to missing .cmd file.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM i.MX53: tqma53: fix console entry ...

The default baseboard for the tqma53 (MBa53) uses UART2 for debug console.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: ccmx51: Another fix SDRAM size detection ...

For CCMX51-boards now we do not use ESDCTL, but actual command for
adding memory is missing. This patch fix this issue.

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

MXS: fix SoC detecting ...

The missing 'break' statement lets look an i.MX23 like an i.MX28.

Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX: ccxmx51: detect SDRAM size by board id ...

This partly reverts:

commit 697e02b
Author: Alexander Shiyan <shc_work@mail.ru>
Date:   Tue Jan 22 15:08:31 2013 +0400

    ARM: ccmx51: Remove SDRAM size settings

    This patch removes SDRAM memory size setting from board due
    to auto detect last one by ESDCTL.

    Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
    Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

The board originally configured the SDRAM controller for the
maximum size and detected the usable SDRAM size by reading the
board id. This became broken after switching to automatic SDRAM
size detection by reading back ESDCTL values.

This patch brings back the old behaviour.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX: Allow disabling SDRAM autodetection ...

Some boards setup more memory than they actually have. The real memory
size can then be detected later for example by reading a board id.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

sama5d3xek: correct rootfs nand partition ...

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: invalidate data caches during early init ...

Some SoCs come up with invalid entries in the data cache. This can
lead to memory corruption when we enable them later, so invalidate
the caches early.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Tested-by: Lucas Stach <l.stach@pengutronix.de>

ARM v7: added v7_mmu_cache_invalidate() ...

At least the iMX6 boot rom seems to jump into barebox with a non
invalidated d-cache which causes data corruption when
v7_mmu_cache_flush() executed by arm_early_mmu_cache_flush() overrides
stack or other valid data.

That's why the cache must be invalided for this processors explicitly
(e.g. in barebox_arm_reset_vector()).  Operation differs from flush only
in one instruction so that patch modifies the existing
v7_mmu_cache_flush() function slightly by adding an optional argument.

Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM v7: v7_mmu_cache_flush(): do not restore r0-r3 (minor optimization) ...

Registers 'r0' till 'r3' are scratch registers and do not need to be
restored.

Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

arm: properly init alignment trap bit ...

On ARMv7 the intention is to disable the alignment trap to be able to
use hardware assisted unaligned load/stores. Fix the init to do the
right thing.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM v7: fix mmu-off operation ...

Although conclusions in 50d1b2d "ARM
v7: Fix register corruption in v7_mmu_cache_off" are correct, the
implemented fix is not complete because the following failure can
happen:

1. d-cache contains the cache line around 'sp'

2. v7_mmu_cache_off() disables cache

3. early v7_mmu_cache_flush() pushes 'lr' on uncached stack

4. v7_mmu_cache_flush() flushes d-cache and can override stack written
   by step 3.

5. v7_mmu_cache_flush() pops 'lr' out of cache and jumps to it which
   might be random data now.

Patch avoids step 3 which is easy because 'lr' is never modified by the
function.  By using the 'r12' scratch register instead of 'r10', the
whole initial 'push' can be avoided.

Patch moves also the 'DMB' operation so that it is executed after data
has been pushed on stack.

Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

fdt: Fix dt memreserve entry ...

The fdt reserve map needs address/size values, not address/end values
like accidently done for generating the reserve entry for the dt.

Reported-by: Jürgen Beisert <j.beisert@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: fix the memset fix ...

From Kernel commit 418df63a ARM: 7670/1: fix the memset fix

| Commit 455bd4c430b0 ("ARM: 7668/1: fix memset-related crashes caused by
| recent GCC (4.7.2) optimizations") attempted to fix a compliance issue
| with the memset return value.  However the memset itself became broken
| by that patch for misaligned pointers.
|
| This fixes the above by branching over the entry code from the
| misaligned fixup code to avoid reloading the original pointer.
|
| Also, because the function entry alignment is wrong in the Thumb mode
| compilation, that fixup code is moved to the end.
|
| While at it, the entry instructions are slightly reworked to help dual
| issue pipelines.
|
| Signed-off-by: Nicolas Pitre <nico@linaro.org>
| Tested-by: Alexander Holler <holler@ahsoftware.de>
| Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

defaultenv-2: Fix settings entry ...

There is no "settings-entries-edit" command. This results in a recursive call
to the settings menu. Use the missing "boot-entries-edit" command instead.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Release v2013.05.0 ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clkdev: fix typo ...

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

common/partition: check only for partition table types ...

The detection of the partition table fails when we have a barebox image
in the MBR. So check only for partition table types.

Signed-off-by: Hubert Feurstein <h.feurstein@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

common/filetype: move partition-table detection into own function ...

Signed-off-by: Hubert Feurstein <h.feurstein@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

MXS/MCI: don't touch variables in the host structure ...

MMC_BUS_WIDTH_* macros do not correspond with the real bus width.
After setting a bus width larger than 1 bit the next call to change the
frequency ends in the default handler and the host interface stays silently
at the previous frequency.

Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: ccxmx51: Fix OTG Host USB mode ...

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

of: fix typos ...

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

of: property: fix error message ...

At least in standard oxford english one not is enough.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

of: fix how an initrd is passed to Linux ...

Linux expects linux,initrd-end to contain the first unused address. As
this doesn't match the end semantic used by barebox (i.e. end contains
the last used address) adding one is necessary.

Without this change Linux fails for me to correctly extract a gzipped
cpio archive provided as initrd.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM i.MX28: make chip reset via reset pin work again ...

Since commit:

    2ccd451 ARM i.MX28: change default watchdog reset method

the external reset via the reset pin is broken. That commit overwrites the
HW_CLKCTRL_RESET register with only WDOG_POR_DISABLE set, which results in
disabling the external reset.

This patch uses read-modify-write to set the WDOG_POR_DISABLE, leaving the
WDOG_POR_DISABLE untouched.

Cc: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>