Merge branch 'for-next/dts'

Merge branch 'for-next/arm'

dts: update to v5.5-rc6 ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

dts: update to v5.5-rc5 ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Release v2020.01.0 ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

usb: ehci: Do not use memset on dma coherent memory ...

memset is an optimized operation that at least on ARM64 may only be
called on cached memory, see 32e8842c40 ("ARM: lib64: Make string
functions aware of MMU configuration"). To avoid crashes in the ehci
driver we no longer call memset on memory allocated with
dma_alloc_coherent(), but use a simple memzero32 function instead.

Reported-by: Elmar Albert <EAlbert@data-modul.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

dts: update to v5.5-rc3 ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: cache_64: invalidate icache in arm_early_mmu_cache_flush ...

So far arm_early_mmu_cache_flush has only been used in preparation for
executing newly-written code. For this reason, on ARMv7 and below,
it had always invalidate the icache after the dcache flush.
We don't do this on ARM64, but sync_caches_for_execution depends on this,
which had this comment that didn't hold true for ARM64:

> Despite the name arm_early_mmu_cache_flush not only flushes the
> data cache, but also invalidates the instruction cache.

It might be worthwhile to decouple dcache flushing from icache
invalidation, but for now, align what we do on ARM64 with what we do for
32-bit ARMs.

This fixes a potential read of stale instructions when loading
second-stage barebox from the PBL with MMU disabled.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: cache_64: invalidate dcache in arm_early_mmu_cache_invalidate ...

On some ARM cores, cache contents are indeterminate after a Power-On
Reset. Turning on the MMU on such cores risks interpreting random cache
lines as valid, causing hard-to-debug errors.

For this reason, we always invalidate the dcache on <= ARMv7. Let's do
likewise for ARM64. Newer ARM cores tend to come up with their dcaches
invalidated already, but for some, like the Cortex-A72, L2 caches are
invalidated dependent on a signal sampled at reset, so better play
it safe.

The icache invalidate here seems to serve no useful purpose. It's kept
for now for symmetry with ARM32.

Note that this is wrong should barebox be entered with the MMU enabled,
but this is so far not the case with any ARM64 platform we support.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM64: entry: save/restore potentially clobbered registers ...

While the comment is correct that currently arm_early_mmu_cache_invalidate()
is only a call to to v8_invalidate_icache_all() , which doesn't clobber x0-x2,
this starts to fall apart as soon as we do something more in this function.

Make sure to properly save/restore the parameters passed to the entry function.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

lds: align RO_DATA_SECTION members ...

When using the RO_DATA_SECTION macro, all the individual components
are put into the rodata section. As they now end up in the same
section there is no alignment enforced between them anymore. This
leads to unaligned start pointers when any of the components have a
unaligned size. Enforce some alignment between them.

Fixes: c5d38e920101 (lds: Add and use RO_DATA_SECTION macro)
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: aarch64: Add support for passing initrd to Linux ...

This adds basic support for passing intird to Linux

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX: Fix PBL size test ...

MAX_PBL_MEMORY_SIZE needs the start symbol name without any suffix. Fix
this to make the PBL size tests effective.

Reported-by: Ulrich Ölmann <u.oelmann@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

dts: update to v5.5-rc2 ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

dts: update to v5.5-rc1 ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

dts: update to v5.4 ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/zynq'

Merge branch 'for-next/watchdog'

Merge branch 'for-next/usb'

Merge branch 'for-next/stm32'

Merge branch 'for-next/shebang'

Merge branch 'for-next/sdhci'

Merge branch 'for-next/randfixes'

Merge branch 'for-next/pci'

Merge branch 'for-next/misc'

Merge branch 'for-next/layerscape'

Merge branch 'for-next/imx'

Merge branch 'for-next/gpio'

Merge branch 'for-next/fsl-fman'

Merge branch 'for-next/dts'