Merge branch 'for-next/net'

Merge branch 'for-next/mvebu'

Merge branch 'for-next/misc'

Merge branch 'for-next/imx'

Merge branch 'for-next/efi'

Merge branch 'for-next/dts'

Merge branch 'for-next/arm'

ARM: i.MX7: Add PSCI support ...

This adds the SoC specific PSCI bits for i.MX7. Based on the
corresponding U-Boot code.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Add PSCI support ...

This patch contains the barebox implementation for the ARM
"Power State Coordination Interface" (PSCI).

The interface is aimed at the generalization of code in the following
power management scenarios:
* Core idle management.
* Dynamic addition and removal of cores, and secondary core boot.
* big.LITTLE migration.
* System shutdown and reset.

In practice, all that's currently implemented is a way to enable the
secondary core one some SoCs.

With PSCI the Kernel is either started in nonsecure or in Hypervisor
mode and PSCI is used to apply power to the secondary cores.

The start mode is passed in the global.bootm.secure_state variable. This
enum can contain "secure" (Kernel is started in secure mode, means no
PSCI), "nonsecure" (Kernel is started in nonsecure mode, PSCI available)
or "hyp" (Kernel is started in hyp mode, meaning it can support
virtualization).

We currently only support putting the secure monitor code into SDRAM,
which means we always steal some amount of memory from the Kernel.
To keep things simple for now we simply keep the whole barebox binary in
memory

The PSCI support has been tested on i.MX7 only so far. The only
supported operations are CPU_ON and CPU_OFF.

The PSCI and secure monitor code is based on the corresponding U-Boot
code.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

config: Set UART port 2 as debug port ...

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

serial: ns16550: Set read/write functions depending on reg-io-width ...

Set proper register read/write functions depending on reg-io-width
device tree property.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: phycore-rk3288: Use UART2 as debug output ...

RK3288's UART2 is the default debug uart interface.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

dts: update to v4.10-rc6 ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

dts: update to v4.10-rc5 ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

dts: update to v4.10-rc4 ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Release v2017.02.0 ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: start: Fix image size calculation ...

In barebox_non_pbl_start() we do not run at the address we are linked
at, so we must read linker variables using ld_var(). Since ld_var()
current is not available on arm64 we create two zero sized arrays,
one at the begin of the image and one at the end. The difference
between both is the image size we are looking for.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Add smc call support ...

Taken from the Kernel: A wrapper to make a smc call from C.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Add UNWIND macro ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

i.MX: vf610: Add support for ZII VF610 Dev Family ...

Add support for ZII VF610 Dev based designs such as:

    - VF610 Dev, revision B
    - VF610 Dev, revision C
    - CFU1, revision A
    - SPU3, revision A
    - SCU4 AIB, revision C

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX7: Initialize CSU ...

The CSU needs to be initialized, otherwise we cannot access memory
in non secure mode.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX7: Add imx7s.dtsi ...

Needed for compiling the i.MX7 warp board which already includes this
file.

This file is necessary because the upstream dtsi file currently assigns
MX7D_CLK_DUMMY to the gpt1 clock we use, so we won't get a meaningful
clock rate.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

pinctrl: i.MX7: Fix LPSR sel_imput setting ...

The i.MX7 has two pinmux controllers, the regular and the LPSR
controller. The LPSR pinmux controller doesn't have any sel_input
registers, instead they can be found in the regular pinmux controller.
This means whenever we want to apply the the sel_input setting for
the LPSR controller, we have to apply them to the regular controller
instead.
In barebox take the easy way out and just add the difference of the
two base addresses to the register offset. The same issue is present
in the Kernel aswell, but when the bootloader already configured
the pins correctly nobody notices when the Kernel sel_input setup
effectively is a no-op.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: start: Fix boarddata allocation ...

It's essential that we always pass the same size value to
arm_mem_barebox_image(), otherwise the result will be inconsistent.
Pass arm_barebox_size instead of barebox_image_size as the latter
does not contain the max bss segment size.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: i.MX7: setup ethernet clocks ...

Reparent ethernet clocks so that they can be used by the
fec driver. The values are the same as U-Boot uses.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: i.MX7: do not register PLL bypass clocks as separate clocks ...

In the Kernel the bypass bits in the PLLs are now registered as
separate clocks and are no longer handled in the PLL code. In
barebox we haven't made this step and there currently seems to
be no reason to do so.
This means that the bypass bits are currently modified in both
the PLL driver and in the separate clocks which does not work
properly. Drop all the bypass clocks to let the bypass bits
be handled in the PLL driver exclusively.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: i.MX7: Fix ethernet clocks ...

The original clock code from Linux registers some gates at
base + 0x44e0, 0x44f0, 0x4500, 0x4510. These are not in the reference
manual and do not seem to have any effect on the hardware. The
reference manual lists clocks at 0x4700 and 0x4710 which Linux
does not control at all. These clocks really do have an effect on
the hardware and are needed for ethernet support. Register the
existing clocks rather than the made up clocks to support
ethernet.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: Add support for shared gates ...

Sometimes a single software control knob controls multiple gates
in hardware. This patch adds support for shared gates which help
coping this situation. The first gate is registered with the hardware
gate as usual, the others are registered as shared gates which does
not have hardware control itself, but only switches the real hardware
gate.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: i.MX7: do clock reparenting when all clocks are initialized ...

By the time the i.MX7 clock driver probes the fixed clocks which
are the roots of the clock tree are not yet present, so reparenting
especially to one of the fixed clocks does not work. Move the
tree setup to a later initcall when the fixed clocks are there.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: i.MX: Pass CLK_OPS_PARENT_ENABLE where necessary ...

CLK_OPS_PARENT_ENABLE was missing on some i.MX7 specific clocks.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>