Merge branch 'for-next/console'

Merge branch 'for-next/canon'

Merge branch 'for-next/arm'

Merge branch 'for-next/am335x'

Release v2014.08.0 ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: AM335x: Beaglebone: enable ethernet ...

The ethernet mac and mdio nodes must be explicitly enabled to override
the disabled setting in am33xx.dtsi.

Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: atmel: sama5d3_xplained: import smc timing from U-Boot ...

The configuration for NAND has been aligned with values
from U-Boot and completed with TIMINGS initialization

Signed-off-by: Matteo Fortini <matteo.fortini@gmail.com>
[voice.shen@atmel.com: apply this patch from Matteo Fortini for
		       sama5d3xek to sama5d3_xplained board]
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Documentation: add QEMU Canon A1100 barebox mini-howto ...

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: DIGIC: add canon-a1100_defconfig ...

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: add Canon A1100 ROM image generation ...

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: AM3355x: Update defconfig ...

Most diffstat comes from refreshing the config. The only real change
is that the NAND xload update handler is enabled now.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mtd: omap gpmc: fix bch8 nand-ecc-opt property ...

We interpret the ECC option "bch8" as OMAP_ECC_BCH8_CODE_HW, but the
Kernel uses OMAP_ECC_BCH8_CODE_HW_ROMCODE in this case instead. To make
the interpretation of the ti,nand-ecc-opt property compatible to the
Kernel we have to use OMAP_ECC_BCH8_CODE_HW_ROMCODE for "bch8"

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mtd: omap gpmc: reserve 14 byte/subpage for ECC in BCH8 romcode ...

As done in the Kernel. The Kernel has a comment this is done to
be compatible with the ROM code.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mtd: omap gpmc: fix ecc bytes/size ...

The ecc bytes / size are per subpage, not per page.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: phyCORE-am335x: Add support for more SDRAM configurations ...

This adds support for 256MB and 128MB RAM configurations of the
phyCORE-AM335x. This is done as new images.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: phyCORE-am335x: read back SDRAM controller settings ...

- use am335x_barebox_entry() to remove the need for hardcoded SDRAM
  size
- remove hardcoded memory settings from device tree since there are
  different memory sizes available for this board.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: AM33xx: Add SDRAM size detection ...

This adds a function which reads back the SDRAM controller settings.
This is used in a AM33xx specific barebox entry function and a
SDRAM driver which registers a SDRAM memory bank.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

of_partition: devfs_add_partition returns an error pointer ...

Check for the return value of devfs_add_partition with IS_ERR.
Otherwise we dereference a NULL pointer when devfs_add_partition
fails.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: am335x Phytec phyCORE: Enable ethernet ...

With an update of the am33xx.dtsi (commit 9313920df6) the mdio and mac
nodes are not enabled on default any more. Enable them explicit
in the board dts now.

Signed-off-by: Teresa Gámez <t.gamez@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

sama5d3x: HSMC NAND initialize TIMINGS and import values from U-Boot ...

The configuration for NAND has been aligned with values
from U-Boot and completed with TIMINGS initialization

Signed-off-by: Matteo Fortini <matteo.fortini@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

sama5d3x: fix HSMC MODE register offset and add TIMINGS register ...

As stated in section 29.19.35 of SAMA5D3 Series Datasheet,
MODE register has offset 0x10 and at offset 0x0C there is
a TIMINGS register.

Signed-off-by: Matteo Fortini <matteo.fortini@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

images: get rid of remaining imximage-y ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: DIGIC: add Canon PowerShot A1100 IS support ...

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

gpio: add driver for Canon DIGIC ...

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

serial: add driver for Canon DIGIC UART ...

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clocksource: add driver for Canon DIGIC timer ...

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: add very initial support for Canon DIGIC chips ...

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: add ARM946E-S CPU type ...

ARM946E-S is used in the DIGIC family SoCs.

ARM946E-S core supports ARMv5TE and has Cache & MPU.
Linux kernel uses ARMv4 MPU cache routines for ARM946E-S core.
E.g. see linux.git/boot/compressed/head.S:

    .word   0x41009400              @ ARM94x
    .word   0xff00ff00
    W(b)    __armv4_mpu_cache_on
    W(b)    __armv4_mpu_cache_off
    W(b)    __armv4_mpu_cache_flush

So select CPU_32v4T for ARM946E-S despite of ARMv5TE support.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: clock: fix the pllb checking ...

On at91sam9n12 soc, it has pllb, while on sama5d3 soc,
it doesn't has pllb.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

fs: ext4: le32_to_cpu() used on a 16-bit field ...

From U-Boot commit:

| commit 8b415f7
| Author: Rommel Custodio <sessyargc+uboot@gmail.com>
| Date:   Sun Jul 21 10:53:25 2013 +0200
|
|     ext4fs: le32_to_cpu() used on a 16-bit field
|
|     Fix reading ext4_extent_header struture on BE machines.  Some 16 bit
|     fields where converted to 32 bit fields, due to the byte swap on BE
|     machines the containing value was corrupted. Therefore reading ext4
|     filesystems on BE machines where broken before.
|
|     Signed-off-by: Rommel Custodio <sessyargc+uboot@gmail.com>
|     [sent via git-send-email; rework commit message]
|     Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
|     Reviewed-by: Simon Glass <sjg@chromium.org>
|     Tested-by: Simon Glass <sjg@chromium.org>
|     Tested-by: Lukasz Majewski <l.majewski@samsung.com>

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>