Merge branch 'for-next/socfpga'

Merge branch 'for-next/pci'

Merge branch 'for-next/net'

Merge branch 'for-next/mvebu'

Merge branch 'for-next/misc'

Merge branch 'for-next/mips'

Merge branch 'for-next/imx'

Merge branch 'for-next/dts'

Merge branch 'for-next/defconfig-update'

Merge branch 'for-next/arm'

Release v2016.11.0 ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

of: of_find_path: Add support for new partition binding ...

The partitions now may be in a subnode of the actual device node.
Eventually go another step up in the hierarchy if required.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

of: partitions: Support new binding ...

The new binding recommends to put the partitions into a subnode
with compatible "fixed-partitions". Add support for this binding.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mtd: spi-nor: add MX25U2033E ...

This chip can be found in 4th generation Kindle devices

Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mtd: nand: nand_mxs: Fix readtotal calculation ...

The calculation of readtotal must be bit alligend. If not the bch core
finds bit flips in every page, because readtotal is too small.
This bug was mostly introduced since commit "51061a9 mtd: nand: nand_mxs:
Add subpage read support".

Tested with:
nand: NAND device: Manufacturer ID: 0x01, Chip ID: 0xd3 (AMD/Spansion
S34ML08G2), 1024MiB, page size: 2048, OOB size: 128

nand: NAND device: Manufacturer ID: 0x2c, Chip ID: 0xdc (Micron
MT29F4G08ABADAWP), 512MiB, page size: 2048, OOB size: 64

nand: NAND device: Manufacturer ID: 0xec, Chip ID: 0xd3 (Samsung NAND
1GiB 3,3V 8-bit), 1024MiB, page size: 2048, OOB size: 64

Signed-off-by: Christian Hemp <c.hemp@phytec.de>
Signed-off-by: Stefan Lengfeld <s.lengfeld@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mtd: Make UBI detection more robust ...

When we want to detect if a mtd device contains an UBI image then
testing the first block is not enough since it can always happen that
UBI has just erased the block before the power failed during last boot.
Since UBI only ever erases one block at a time and directly writes the
ec header to it afterwards, it shouldn't be necessary to scan the whole
device for UBI data. Scan the first 64 blocks. The first non-empty block
then must contain UBI data, if instead we find foreign data we assume
that no UBI is on that mtd device.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

nand: imx6: Changed default NAND clock ...

The Barebox recognized false bad erase blocks while booting from a
Spansion NAND (1). This error occurred due a to high clock. The
Kernel sets the default NAND clock to 22Mhz. So, to fix this error and
to be more identical with the Kernel, the Barebox should be too.

1: nand: NAND device: Manufacturer ID: 0x01, Chip ID: 0xd3 (AMD/Spansion
S34ML08G2), 1024MiB, page size: 2048, OOB size: 128

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Tested-by: Stefan Lengfeld <s.lengfeld@phytec.de>
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

net/designware: add explicit reset of {tx|rx}_currdescnum ...

Driver "init" function might be called multiple times.
On every "init" Tx/Rx buffer descriptors are initialized: "descs_init"
-> "{tx|rx}_descs_init".

In its turn those init functions set MAC's "{tx|rx}desclistaddr" to
point on the first buffer descriptor in the list.

So CPU to start operation from the first buffer descriptor as well after
every "init" we have to reset "{tx|rx}_currdescnum".

[Original U-Boot patch by Alexey Brodkin <abrodkin@synopsys.com>]

Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

net: designware: Respect "bus mode" register contents on SW reset ...

"bus mode" register contains lots of fields and some of them don't
expect to be written with 0 (zero). So since we're only interested in
resetting MAC (which is done with setting the least significant bit of
this register with "0") I believe it's better to modify only 1 bit of
the register.

[Original U-Boot patch by Alexey Brodkin <abrodkin@synopsys.com>]

Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

net/designware: Do not select MIIPORT for RGMII interface ...

Do not select MIIPORT for RGMII interface

[Original U-Boot patch by Vipin Kumar <vipin.kumar@st.com>]

Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

net/designware: Consecutive writes to the same register to be avoided ...

There are a few registers where consecutive writes to the same location
should be avoided or have a delay.

According to Synopsys, here is a list of the registers and bit(s) where
consecutive writes should be avoided or a delay is required:

DMA Registers:
Register 0        Bit 7
Register 6        All bits except for 24, 16-13, 2-1.

GMAC Registers:
Registers 0-3     All bits
Registers 6-7     All bits
Register 10       All bits
Register 11       All bits except for 5-6.
Registers 16-47   All bits
Register 48       All bits except for 18-16, 14.
Register 448      Bit 4.
Register 459      Bits 0-3.

[Original U-Boot patch by Dinh Nguyen <dinguyen@altera.com>]

Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: add clock command completion ...

This adds tab completion for the clk_* commands.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX6 esdctl: Add i.MX6ul support ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX: ocotp: Add i.MX6ul support ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

serial: i.MX: Add i.MX6ul support ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

pinmux: imx-iomux-v3: Add i.MX6ul support ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX6 gpt: Add i.MX6ul support ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX6ul: Add clock support ...

Nearly identical to Linux-4.8 clock support, only some unnecessary
clocks skipped.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX: beginning i.MX6ul support ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX: OCOTP: Add functions to access fuses field wise ...

Add functions to access the OCOTP fuses field wise, similar to what has
been done for the IIM. Also add a i.MX6 fusemap header file.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>