ARM: i.MX6 Wandboard Quad: fix PBL UART MUX ...

Three variants of the Wandboard exist: WBSOLO, WBDUAL and WBQUAD.
For all variants, the external serial port is connected to UART1 via
PAD_CSI0_DATA10 (TX) and PAD_CSI0_DATA11 (RX). Unfortunately, the IOMUX
register adresses for this mux differ between i.MX6Q (WBQUAD) and others.
Make the UART IOMUX for PBL compatible for WBQUAD.

Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX6 Wandboard: dont do MMDC Write Leveling Calibration ...

The hardware requirements to perform a write leveling calibration are
not fulfilled by the Wandboard modules.
IMX6DQRM §44.11.6 "Write leveling Calibration" Note2 states that the first
bit of each data byte group (D0, D8, ..., D56) from memory must be connected
to the same data bus bit on the controller, which is not given on the
Wandboard modules, resulting in unpredictable calib results and breaking the
WBQUAD 2GiB SDRAM setup. Similar restrictions exist for the i.MX6SD.

Remove this calibration and use the MPWLDECTRL defaults.

Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

i.MX/WD: setup the watchdog according to its datasheet ...

From earlier SoCs like the i.MX21 up to i.MX7 their datasheets states
after reset the watchdog timer has to be set first prior enabling the
watchdog itself. This change do it this way.

Signed-off-by: Juergen Borleis <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX6: add Technexion Pico Hobbit support ...

This adds support for the i.MX6UL Technexion Pico Hobbit. The board
comes with different amounts of RAM. We create one image for the 256MB
and one for the 512MB variant.

Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
   ---
   v1 -> v2: - removed already prepared clock setup
   v2 -> v3: - added phy-reset-post-delay as the support is now available

Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

i.MX: fec: add post PHY reset delay DT property ...

Some PHY require to wait for a bit after the reset GPIO has been
toggled. This adds support for the DT property `phy-reset-post-delay`
which gives the delay in milliseconds to wait after reset.

If the DT property is not given, no delay is observed. Post reset
delay greater than 1000ms are invalid.

Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: phytec-som-imx6: remove needles enet refclk setup ...

All REF_CLK output setup now is generically prepared for imx6ul. The
handling of the ENET_CLK_SEL (gpr[13]|gpr[14]) bits is not necessary, as
0 is their reset value.

Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX: setup ENET_TX_CLK_DIR in imx6_init for every imx6ul ...

We generically enable the output of ENET_TX_CLK.
It will be output if ENET_REF_CLK is selected.

Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: imx6: gw54xx: use wdog1 for barebox ...

As Barebox isn't changing the external PMIC power rails the internal
watchdog reset is fine for the Barebox reset purposes. Watchdog 2 is
only usable on boards with revision E or later, as this on is incapable
of executing an internal reset.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: imx6: gw54xx: fixup watchdog nodes on pre rev E boards ...

Older boards before revision E don't have the external watchdog signal
wired up to the PMIC, so they must use watchdog 1, which is able to
reset the SoC internally.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: imx6: gw54xx: add function to retrieve board revision from GSC ...

This parses the board revision from the GSC EEPROm model string.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

imx-bbu-nand-fcb: add support for imx6ull ...

The i.MX 6ull secures the fcb with bch 40. This is identical to i.MX 6ul.

Signed-off-by: Christian Hemp <c.hemp@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARCH: ARM: Add support for phytec-phycore-imx6ull ...

Created imx6ull devicetree to support Phytec phyCORE-i.MX6ULL.
 - 256 MB RAM
 - 128 MB NAND
 - 10/100 Mbit Ethernet

Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX6ul: Add Clock support for i.MX6ull ...

From linux-4.10 clock support, only skipped some unnecessary clocks

Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX: Add i.MX6 ULL support ...

Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX: HAB: update documentation of command sequence files (CSF) ...

Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: mx6sx-sabresdb: the ethernet clocks get enabled by fec_imx ...

All necessary clocks get already enabled through the fec_imx driver
configured by the devicetree.

Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: phytec-som-imx6: the ethernet clocks get enabled by fec_imx ...

All necessary clocks get already enabled through the fec_imx driver
configured by the devicetree.

Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

i.MX: fec: also enable optional clocks ...

This will also enable two more optional clocks. They can be found on
mx6ul, mx6sx and mx28.

Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clock: initialize dummy clocksource statically ...

Assigning the dummy clocksource in a initcall has the problem that
get_time_ns() crashes before that initcall is executed. This happens
when dmesg support is enabled in conjunction with CONFIG_DEBUG_INITCALLS.
In this case the dmesg code wants to have the timestamp of a log
message.
Solve this by setting the current clocksource to the dummy clock
statically and not at runtime. This way we always have a dummy
clock available.

Fixes:
commit 8972eb7
Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Date:   Fri Mar 3 13:34:02 2017 +0100

    clocksource: move dummy clock source to init_clock

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/state'

Merge branch 'for-next/socfpga'

Merge branch 'for-next/parameter-types'

Merge branch 'for-next/omap'

Merge branch 'for-next/mvebu'

Merge branch 'for-next/misc'

Merge branch 'for-next/libgen'

Merge branch 'for-next/imx'

Merge branch 'for-next/dts'

Merge branch 'for-next/arm'

imx-bbu-nand-fcb: add support for imx6ul ...

imx6ul secure the fcb with bch 40. The imx-kobs tool use a own modified
bch lib. They reverse the bit order of the data and the ecc.
To use the bch lib in barebox the bytes in the data buffers must be
reversed.
The data layout on nand is bit aligned. But with 40 bits this is not an
issue for imx6ul now.

Signed-off-by: Jan Remmet <J.Remmet@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>