sama5d3x: HSMC NAND initialize TIMINGS and import values from U-Boot ...

The configuration for NAND has been aligned with values
from U-Boot and completed with TIMINGS initialization

Signed-off-by: Matteo Fortini <matteo.fortini@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

sama5d3x: fix HSMC MODE register offset and add TIMINGS register ...

As stated in section 29.19.35 of SAMA5D3 Series Datasheet,
MODE register has offset 0x10 and at offset 0x0C there is
a TIMINGS register.

Signed-off-by: Matteo Fortini <matteo.fortini@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

led: triggers: fix "no previous prototype for 'trigger_init'" warning ...

Here is compiler's message:

    drivers/led/led-triggers.c:148:5: warning: no previous prototype for 'trigger_init' [-Wmissing-prototypes]
    int trigger_init(void)
        ^

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

commands: trigger: check trigger disable return code too ...

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

led: triggers: fix crash on disabling "default-on" trigger ...

Here is a sample crash log on Ritmix RZX-50:

    barebox:/ trigger
    0: panic
    1: heartbeat
    2: net rx
    3: net tx
    4: net
    5: default on (led 0)
    barebox:/ trigger -d 5
    ...
    Ooops, TLB miss on store!

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

MIPS: ritmix-rzx50_defconfig: enable LED-related stuff ...

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

MIPS: dts: rzx50.dts: add LCD backlight ...

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

i2c: busses/Makefile: fix indentation ...

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

i2c: add Marvell 64xxx driver ...

This driver is also used for Allwinner SoCs I2C controllers.

Ported from linux-3.15.

The most notable barebox driver version changes:

  * drop platform device stuff;
  * drop "allwinner,sun*" stuff;
  * drop message offloading support;
  * add reg-io-width devicetree parameter to use driver
    with byte-oriented controller versions.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
On Armada XP:
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

net: phy: Add minimal support for QSGMII PHY ...

Based on Linux's support by Thomas Petazzoni:

    commit b9d1208
    Author: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
    Date:   Tue Apr 15 15:50:19 2014 +0200
    net: phy: add minimal support for QSGMII PHY

    This commit adds the necessary definitions for the PHY layer to
    recognize "qsgmii" as a valid PHY interface. A QSMII interface, as
    defined at
    http://en.wikipedia.org/wiki/Media_Independent_Interface#Quad_Serial_Gigabit_Media_Independent_Interface,
    is "is a method of combining four SGMII lines into a 5Gbit/s
    interface. QSGMII, like SGMII, uses LVDS signalling for the TX and RX
    data and a single LVDS clock signal. QSGMII uses significantly fewer
    signal lines than four SGMII busses."

    This type of MAC <-> PHY connection might require special handling on
    the MAC driver side, so it should be possible to express this type of
    MAC <-> PHY connection, for example in the Device Tree.

    Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
    Cc: devicetree@vger.kernel.org
    Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
    Signed-off-by: David S. Miller <davem@davemloft.net>

Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

net: phy: mdio-mvebu: Make the clock property required ...

This property is wrongly documented as 'optional', although all the
ethernet units need a clock to be enabled in order to access the MDIO
interface. For that reason, this commit makes the property a required
one and fails to probe the device, when a clock is not properly provided.

Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

net: phy: Add fallbacks for the obsoletes phy DT properties ...

In addition to the standard 'phy-handle' devicetree property, the binding
specifies two properties, which are considered obsolete: 'phy' and 'phy-device'.
This commit adds support for them in of_mdio_find_phy().

Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Add a simple rtc framework ...

This patch adds a simple rtc framework
for reading and setting board's RTC time.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

lib: import 'bcd' from linux-3.15 ...

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

pci: mvebu: Add PCIe driver ...

This adds a PCI driver for the controllers found on Marvell MVEBU SoCs.
Besides the functional driver itself, it also adds SoC specific PHY
setup required for PCIe. Currently, only Armada 370 is fully supported.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

of: pci: import of_pci_get_devfn() ...

Marvell MVEBU PCIe driver requires of_pcie_get_devfn(), import it from
Linux.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

pci: set auto-incremented bus number ...

When using more than one PCI bus, we have to assign unique numbers
to each bus. Use an auto-incremented bus index and assign it to
each registered bus. Also, allow the PCI host controller to update
internal registers by calling set_busno with assigned bus number.

While at it, add pci_controller struct to set_busno callback,
add a back reference to pci_controller to pci_bus, and clean up
unused left-overs from Linux import.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

pci: ensure device does ignore BAR mangling ...

Disable access to PCI devices I/O and memory regions while
mangling BAR registers.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

pci: register device after BAR setup ...

As soon as pci_register_device is called, a potential driver
will access its registers. This requires BARs to be set up
properly, so move pci_register_device after BAR setup.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

pci: pci_scan_bus: respect 64b BARs ...

In PCI 64-bit BARs span two 32-bit BARs, therefore if BAR type
indicates a 64-bit BAR we have to skip the next BAR register.
While at it, also set proper IORESOURCE flags for I/O and
32b MEM.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: mvebu: armada-370-xp: disable MBUS error propagation ...

Accessing MBUS windows not backed-up by e.g. PCIe devices will
hang the SoC. Disable MBUS error propagation back to CPU allows
to read 0xffffffff instead of hanging the SoC.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

bus: mvebu: fix resource size handling ...

A resource_size is defined as res->end - res->start + 1. Marvell
MBUS driver gets some ranges from DT as start and size but mis-calculates
end of range. This fixes 4 occurences of those mistakes.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

images: get rid of remaining imximage-y ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: DIGIC: add Canon PowerShot A1100 IS support ...

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

gpio: add driver for Canon DIGIC ...

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

serial: add driver for Canon DIGIC UART ...

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clocksource: add driver for Canon DIGIC timer ...

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: add very initial support for Canon DIGIC chips ...

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: add ARM946E-S CPU type ...

ARM946E-S is used in the DIGIC family SoCs.

ARM946E-S core supports ARMv5TE and has Cache & MPU.
Linux kernel uses ARMv4 MPU cache routines for ARM946E-S core.
E.g. see linux.git/boot/compressed/head.S:

    .word   0x41009400              @ ARM94x
    .word   0xff00ff00
    W(b)    __armv4_mpu_cache_on
    W(b)    __armv4_mpu_cache_off
    W(b)    __armv4_mpu_cache_flush

So select CPU_32v4T for ARM946E-S despite of ARMv5TE support.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

dts: update to v3.16-rc6 ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>