dts: update to v4.10-rc5 ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

dts: update to v4.10-rc4 ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Release v2017.02.0 ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: start: Fix image size calculation ...

In barebox_non_pbl_start() we do not run at the address we are linked
at, so we must read linker variables using ld_var(). Since ld_var()
current is not available on arm64 we create two zero sized arrays,
one at the begin of the image and one at the end. The difference
between both is the image size we are looking for.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Add smc call support ...

Taken from the Kernel: A wrapper to make a smc call from C.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Add UNWIND macro ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

i.MX: vf610: Add support for ZII VF610 Dev Family ...

Add support for ZII VF610 Dev based designs such as:

    - VF610 Dev, revision B
    - VF610 Dev, revision C
    - CFU1, revision A
    - SPU3, revision A
    - SCU4 AIB, revision C

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX7: Initialize CSU ...

The CSU needs to be initialized, otherwise we cannot access memory
in non secure mode.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX7: Add imx7s.dtsi ...

Needed for compiling the i.MX7 warp board which already includes this
file.

This file is necessary because the upstream dtsi file currently assigns
MX7D_CLK_DUMMY to the gpt1 clock we use, so we won't get a meaningful
clock rate.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

pinctrl: i.MX7: Fix LPSR sel_imput setting ...

The i.MX7 has two pinmux controllers, the regular and the LPSR
controller. The LPSR pinmux controller doesn't have any sel_input
registers, instead they can be found in the regular pinmux controller.
This means whenever we want to apply the the sel_input setting for
the LPSR controller, we have to apply them to the regular controller
instead.
In barebox take the easy way out and just add the difference of the
two base addresses to the register offset. The same issue is present
in the Kernel aswell, but when the bootloader already configured
the pins correctly nobody notices when the Kernel sel_input setup
effectively is a no-op.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: start: Fix boarddata allocation ...

It's essential that we always pass the same size value to
arm_mem_barebox_image(), otherwise the result will be inconsistent.
Pass arm_barebox_size instead of barebox_image_size as the latter
does not contain the max bss segment size.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: i.MX7: setup ethernet clocks ...

Reparent ethernet clocks so that they can be used by the
fec driver. The values are the same as U-Boot uses.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: i.MX7: do not register PLL bypass clocks as separate clocks ...

In the Kernel the bypass bits in the PLLs are now registered as
separate clocks and are no longer handled in the PLL code. In
barebox we haven't made this step and there currently seems to
be no reason to do so.
This means that the bypass bits are currently modified in both
the PLL driver and in the separate clocks which does not work
properly. Drop all the bypass clocks to let the bypass bits
be handled in the PLL driver exclusively.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: i.MX7: Fix ethernet clocks ...

The original clock code from Linux registers some gates at
base + 0x44e0, 0x44f0, 0x4500, 0x4510. These are not in the reference
manual and do not seem to have any effect on the hardware. The
reference manual lists clocks at 0x4700 and 0x4710 which Linux
does not control at all. These clocks really do have an effect on
the hardware and are needed for ethernet support. Register the
existing clocks rather than the made up clocks to support
ethernet.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: Add support for shared gates ...

Sometimes a single software control knob controls multiple gates
in hardware. This patch adds support for shared gates which help
coping this situation. The first gate is registered with the hardware
gate as usual, the others are registered as shared gates which does
not have hardware control itself, but only switches the real hardware
gate.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: i.MX7: do clock reparenting when all clocks are initialized ...

By the time the i.MX7 clock driver probes the fixed clocks which
are the roots of the clock tree are not yet present, so reparenting
especially to one of the fixed clocks does not work. Move the
tree setup to a later initcall when the fixed clocks are there.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: i.MX: Pass CLK_OPS_PARENT_ENABLE where necessary ...

CLK_OPS_PARENT_ENABLE was missing on some i.MX7 specific clocks.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: i.MX: clk-gate2: Allow to pass flags ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: implement CLK_OPS_PARENT_ENABLE ...

Some clocks may only be modified when their parent clocks are enabled.
The kernel has the CLK_OPS_PARENT_ENABLE flag for this purpose.
Implement it for barebox aswell.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: Keep enable count consistent over reparent ...

When reparenting a clock we have to make sure the new parent is enabled
when the clock was enabled on the old parent. Also we have to decrease
the old parents use counter when the clock was enabled.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM i.MX: Add i.MX6SL support ...

Most i.MX6SL infrastructure is already covered in barebox by general i.MX6
support. Missing infrastructure provided in separate commits are
* SoC type detection
* Clock infrastructure

Add the missing fsl,imx6sl-mmdc, so it will not be catched by fsl,imx6q-mmdc
and the remaining bits and pieces to provide barebox i.MX6SL SoC support.

Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX6SL: import clock infrastructure from linux ...

Import i.MX6SL clock infrastructure from linux clk-imx6sl.c

To save space, clocks beeing unlikely usefull for bootloader purposes
(SSI, SPDIF, EXTERN_AUDIO) were not imported.
Further, the fixup code from linux mainline commits
a49e6c4b8204 ("ARM: imx: add common clock support for fixup mux")
cbe7fc8aaeef ("ARM: imx: add common clock support for fixup div")
was ignored for this commit.

Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM i.MX: add SoC type detection for i.MX6SL ...

The i.MX6 series SoC type is determined by barebox by examining the
USB_ANALOG_DIGPROG aka IMX6_ANATOP_SI_REV register. This register is located
at a common offset for all mx6 SoC - except for i.MX6SL where a different
offset is used. This creates a dilemma while distinguishing the mx6sl from
non-mx6sl SOC since the SoC type identification register location is type
specific itself.

Access to undocumented and probably invalid or unpredictable registers should
be avoided as possible. For the mx6sl detection an access to the general
USB_ANALOG_DIGPROG @0x260 cannot be avoided when running on mx6sl. This
register contained the value 0x00014009 for different mx6sl Rev. 1.2 based
e-book readers using MCIMX6L7DVN10AB and MCIMX6L8DVN10AB SoC. This
implementation assumes the value of MAJOR_UPPER (here 0x01) to be smaller
than the smallest non-6sl MAJOR_UPPER (0x61 for mx6s).

Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM i.MX: move cpu_type macros in front of cpu_revision code ...

Preparational commit to enable the use of cpu_type macros in imx6_cpu_revision()

Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX7: add AIPS base address defines ...

Import the ARM IP bus base addresses from IMX7DRM 05/2016 AIPS Memory Map

Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

spi: i.MX: Add driver for DSPI ...

Add driver for DSPI - SPI IP core found on various Freescale/NXP
products (including Vybrid/VF610).

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

usb: ehci: pass full speed devices to companion controller ...

According to the "Enhanced Host Controller Interface Specification for
Universal Serial Bus" after a USB port reset the EHCI Driver checks the
PortEnable bit in the PORTSC register. If set to a one, the connected device is
a high-speed device [...]. At the time the EHCI Driver receives the port reset
and enable request the LineStatus bits might indicate a low-speed device.
Additionally, when the port reset process is complete, the PortEnable field may
indicate that a full-speed device is attached. In either case the EHCI driver
sets the PortOwner bit in the PORTSC register to a one to release port
ownership to a companion host controller.

Signed-off-by: Peter Mamonov <pmamonov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mtd: spi-nor: add support for s25fl208k ...

Signed-off-by: Peter Mamonov <pmamonov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

arm: am33xx: Initialize EMIF REG_PR_OLD_COUNT ...

This patch is based on a patch from the U-Boot and fixes two errors with
the LCDC. Original commit message from Jyri Sarha [1]:
"Initialize EMIF OCP_CONFIG registers REG_COS_COUNT_1, REG_COS_COUNT_2,
and REG_PR_OLD_COUNT field for Beaglebone-Black and am335x-evm. With
the default values LCDC suffers from DMA FIFO underflows and frame
synchronization lost errors. The initialization values are the highest
that work flawlessly when heavy memory load is generated by CPU. 32bpp
colors were used in the test. On BBB the video mode used 110MHz pixel
clock. The mode supported by the panel of am335x-evm uses 30MHz pixel
clock."

The register values are generated by testing, because there is no formula
to calculate them. Also from Jyri Sarha [1]:
"In practice the only rule to find an optimal value is to find as high as
possible REG_PR_OLD_COUNT value that does not produce LCDC FIFO
underflows under worst case scenario. The worst case happens when the
highest pixel clock videomode with maximum bpp is used while memory
subsystem is stressed by endless stream of writes hitting the same
memory memory bank (can be the same address)."

It only contains the BeagleBone Black and the Phytec SoM, because I
don't have other boards.

[1] https://patchwork.ozlabs.org/patch/704013/

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX7: Kconfig: ARCH_IMX7 selects COMMON_CLK_OF_PROVIDER ...

Build of clk-imx7 depends on selection of COMMON_CLK_OF_PROVIDER

Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>