Release v2017.07.0 ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

pinctrl: at91: Bail out if atmel,pins property does not exist ...

Do not blindly assume that a device node has a atmel,pins property.
Instead, test it for being NULL before using it. This also silences
a compiler warning when the driver is compiled without OF support.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: dts: i.MX6: fix usdhc3 pinmuxing on tqma6x ...

The usdhc3 pin group wrongly referred the SD4 pads instead of the SD3 pads.
This leads to issues when muxing the SD4_CMD and SD4_CLK pads for uart3.

This regression was introduced by code refactoring in commit a5207a6 ("ARM:
dts: i.MX6: drop usage of pin group defines").

Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

i.MX: clk: Remove imx_clk_pllv3_locked() ...

Remove imx_clk_pllv3_locked() which was introduced for the sake of
Vybrid platform. The same effect (waiting on 'locked' bit) can be
achived with vanilla clk_pllv3_enable/disable, which make said
function unnecessary.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

i.MX: clk-pllv3: Do not touch PLL_BYPASS bit ...

Do not touch PLL_BYPASS bit as a part of clk_pll3_enable/disable
execution. For a number of platforms (e.g. Vybrid, i.MX6SL) PLL_BYPASS
is specified as a bit controlling a clock MUX represented by a
dedicated 'struct clk'. Altering that bit as a part of
clk_pll3_enable/disable is equivalent to calling clk_set_parent() and
it makes in the following code:

clk_enable(clk_disable(<some pll>))

change clock chain instead of being a no-op.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk-vf610: Mark all of CCSR muxes with CLK_OPS_PARENT_ENABLE ...

As per VYBRIDRM.pdf, p. 673:

"... When switching clock sources on GL MUX, both active and target
clock sources must be active..."

So mark all of the clock muxes controlled by CCM_CSSR with
CLK_OPS_PARENT_ENABLE to satisfy that requirement. Experiment shows
that failing to do so would result in failure (in some cases CPU
hang).

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

pci: mvebu: terminate error message with a newline ...

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/state'

Merge branch 'for-next/misd'

Merge branch 'for-next/misc'

Merge branch 'for-next/mips'

Merge branch 'for-next/imx'

Merge branch 'for-next/gpio'

Merge branch 'for-next/dts'

Merge branch 'for-next/directory-links'

Merge branch 'for-next/arm'

Revert "nv: Do not create globalvars from nvvars" ...

This reverts commit 35d8e85.

Revert "globalvar: remove code for unqualified globalvars" ...

This reverts commit e4f8105.

Revert "globalvar: make globalvar functions more consistent" ...

This reverts commit 1b4a05c.

Revert "param: remove unnecessary device_d * argument" ...

This reverts commit 0071bac.

Revert "globalvar: don't use nv_device if CONFIG_NVVAR is disabled" ...

This reverts commit b378e8c.

Revert "globalvar: make nv_device static" ...

This reverts commit f655902.

Revert "nv: Fix setting of nv.dev.<devname>.<param> variables" ...

This reverts commit eaf884b.

Revert "globalvar: Fix value of new globalvar when nvvar exists" ...

This reverts commit f8a1774.

Release v2017.06.0 ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX6 Wandboard: add Documentation ...

Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX6 Wandboard: enable Wandboard Quad ...

Extend the DT compatibility check to actually use the Wandboard Quad.

Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX6 Wandboard Quad: fix PBL UART MUX ...

Three variants of the Wandboard exist: WBSOLO, WBDUAL and WBQUAD.
For all variants, the external serial port is connected to UART1 via
PAD_CSI0_DATA10 (TX) and PAD_CSI0_DATA11 (RX). Unfortunately, the IOMUX
register adresses for this mux differ between i.MX6Q (WBQUAD) and others.
Make the UART IOMUX for PBL compatible for WBQUAD.

Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX6 Wandboard: dont do MMDC Write Leveling Calibration ...

The hardware requirements to perform a write leveling calibration are
not fulfilled by the Wandboard modules.
IMX6DQRM §44.11.6 "Write leveling Calibration" Note2 states that the first
bit of each data byte group (D0, D8, ..., D56) from memory must be connected
to the same data bus bit on the controller, which is not given on the
Wandboard modules, resulting in unpredictable calib results and breaking the
WBQUAD 2GiB SDRAM setup. Similar restrictions exist for the i.MX6SD.

Remove this calibration and use the MPWLDECTRL defaults.

Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

watchdog: i.MX: fix i.MX6 reset ...

According to the Errata ERR004346 (WDOG: WDOG SRS bit requires to be written
twice), add another two writes to ensure there must be at least two
writes happen in the same one 32kHz clock period.
Without this two additional writes, the system will not reset always.

Tested with i.MX6Quad and i.MX6 UltraLite

Signed-off-by: Christian Hemp <c.hemp@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>