mtd: devices: m25p80: use the spi_mem_xx() API ...

This is the barebox adoption of the linux v4.16 patch

  4120f8d
  Author:     Boris Brezillon <bbrezillon@kernel.org>
  AuthorDate: Thu Apr 26 18:18:19 2018 +0200
  Commit:     Mark Brown <broonie@kernel.org>
  CommitDate: Fri May 11 11:33:51 2018 +0900

  mtd: spi-nor: Use the spi_mem_xx() API

  The spi_mem_xxx() API has been introduced to replace the
  spi_flash_read() one. Make use of it so we can get rid of
  spi_flash_read().

  Note that using spi_mem_xx() also simplifies the code because this API
  takes care of using the regular spi_sync() interface when the optimized
  ->mem_ops interface is not implemented by the controller.

  Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
  Reviewed-by: Frieder Schrempf <frieder.schrempf@exceet.de>
  Tested-by: Frieder Schrempf <frieder.schrempf@exceet.de>
  Signed-off-by: Mark Brown <broonie@kernel.org>

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mtd: spi-nor: provide default erase_sector implementation ...

Based on the Linux v4.4 patch

commit c67cbb8
Author:     Brian Norris <computersforpeace@gmail.com>
AuthorDate: Tue Nov 10 12:15:27 2015 -0800
Commit:     Brian Norris <computersforpeace@gmail.com>
CommitDate: Thu Nov 19 13:34:44 2015 -0800

    mtd: spi-nor: provide default erase_sector implementation

    Some spi-nor drivers perform sector erase by duplicating their
    write_reg() command. Let's not require that the driver fill this out,
    and provide a default instead.

    Tested on m25p80.c and Medatek's MT8173 SPI NOR flash driver.

    Signed-off-by: Brian Norris <computersforpeace@gmail.com>

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mtd: spi-nor: introduce SPI 1-2-2 and SPI 1-4-4 protocols ...

Sync the driver with Linux v4.12 and apply the patch

  commit cfc5604
  Author:     Cyrille Pitchen <cyrille.pitchen@atmel.com>
  AuthorDate: Tue Apr 25 22:08:46 2017 +0200
  Commit:     Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
  CommitDate: Mon May 15 21:56:17 2017 +0200

      mtd: spi-nor: introduce SPI 1-2-2 and SPI 1-4-4 protocols

      This patch changes the prototype of spi_nor_scan(): its 3rd parameter
      is replaced by a 'struct spi_nor_hwcaps' pointer, which tells the spi-nor
      framework about the actual hardware capabilities supported by the SPI
      controller and its driver.

      Besides, this patch also introduces a new 'struct spi_nor_flash_parameter'
      telling the spi-nor framework about the hardware capabilities supported by
      the SPI flash memory and the associated settings required to use those
      hardware caps.

      Then, to improve the readability of spi_nor_scan(), the discovery of the
      memory settings and the memory initialization are now split into two
      dedicated functions.

      1 - spi_nor_init_params()

      The spi_nor_init_params() function is responsible for initializing the
      'struct spi_nor_flash_parameter'. Currently this structure is filled with
      legacy values but further patches will allow to override some parameter
      values dynamically, for instance by reading the JESD216 Serial Flash
      Discoverable Parameter (SFDP) tables from the SPI memory.
      The spi_nor_init_params() function only deals with the hardware
      capabilities of the SPI flash memory: especially it doesn't care about
      the hardware capabilities supported by the SPI controller.

      2 - spi_nor_setup()

      The second function is called once the 'struct spi_nor_flash_parameter'
      has been initialized by spi_nor_init_params().
      With both 'struct spi_nor_flash_parameter' and 'struct spi_nor_hwcaps',
      the new argument of spi_nor_scan(), spi_nor_setup() computes the best
      match between hardware caps supported by both the (Q)SPI memory and
      controller hence selecting the relevant settings for (Fast) Read and Page
      Program operations.

      Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
      Reviewed-by: Marek Vasut <marek.vasut@gmail.com>

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

spi: add driver for Freescale QSPI controller ...

This is based on the Linux v5.1-rc1 driver introduced with the commit:

  commit 84d0431
  Refs: v5.0-rc1-1-g84d043185dbe
  Author:     Frieder Schrempf <frieder.schrempf@kontron.de>
  AuthorDate: Mon Jan 7 09:29:47 2019 +0000
  Commit:     Mark Brown <broonie@kernel.org>
  CommitDate: Mon Jan 7 16:56:24 2019 +0000

      spi: Add a driver for the Freescale/NXP QuadSPI controller

      This driver is derived from the SPI NOR driver at
      mtd/spi-nor/fsl-quadspi.c. It uses the new SPI memory interface
      of the SPI framework to issue flash memory operations to up to
      four connected flash chips (2 buses with 2 CS each).

      The controller does not support generic SPI messages.

      This patch also disables the build of the "old" driver and reuses
      its Kconfig option CONFIG_SPI_FSL_QUADSPI to replace it.

      Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
      Acked-by: Han Xu <han.xu@nxp.com>
      Reviewed-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
      Tested-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
      Tested-by: Han Xu <han.xu@nxp.com>
      Reviewed-by: Boris Brezillon <bbrezillon@kernel.org>
      Signed-off-by: Mark Brown <broonie@kernel.org>

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mtd: spi-nor: remove unused read_xfer/write_xfer hooks ...

Based on the Linux v4.3 patch:

  commit 79c452a
  Author:     Cyrille Pitchen <cyrille.pitchen@atmel.com>
  AuthorDate: Fri Sep 18 17:49:25 2015 +0200
  Commit:     Brian Norris <computersforpeace@gmail.com>
  CommitDate: Mon Sep 21 16:49:52 2015 -0700

      mtd: spi-nor: remove unused read_xfer/write_xfer hooks

      struct spi_nor_xfer_cfg and read_xfer/write_xfer hooks were never used by
      any driver. Do some cleanup by removing them.

      Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
      Reviewed-by: Marek Vasut <marex@denx.de>
      Signed-off-by: Brian Norris <computersforpeace@gmail.com>

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mtd: spi-nor: remove unused write_enable from write_reg ...

Based on the Linux v4.2 commit:

  commit f9f3ce8
  Author:     Jagan Teki <jteki@openedev.com>
  AuthorDate: Wed Aug 19 15:26:44 2015 +0530
  Commit:     Brian Norris <computersforpeace@gmail.com>
  CommitDate: Fri Sep 11 16:04:55 2015 -0700

      mtd: spi-nor: Zap unneeded write_enable from write_reg

      The 'write_enable' argument is unused and unneeded, so remove it from
      the API.

      Signed-off-by: Jagan Teki <jteki@openedev.com>
      Cc: David Woodhouse <dwmw2@infradead.org>
      Cc: Han Xu <han.xu@freescale.com>
      [Brian: fixed for nxp-spifi.c]
      Signed-off-by: Brian Norris <computersforpeace@gmail.com>

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

spi: Extend the core to ease integration of SPI memory controllers ...

Sync with Linux v5.1-rc1.

This is the barebox adoption of the commit

  commit c36ff26
  Author: Boris Brezillon <boris.brezillon@bootlin.com>
  Date:   Thu Apr 26 18:18:14 2018 +0200

      spi: Extend the core to ease integration of SPI memory controllers

      Some controllers are exposing high-level interfaces to access various
      kind of SPI memories. Unfortunately they do not fit in the current
      spi_controller model and usually have drivers placed in
      drivers/mtd/spi-nor which are only supporting SPI NORs and not SPI
      memories in general.

      This is an attempt at defining a SPI memory interface which works for
      all kinds of SPI memories (NORs, NANDs, SRAMs).

      Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
      Reviewed-by: Frieder Schrempf <frieder.schrempf@exceet.de>
      Tested-by: Frieder Schrempf <frieder.schrempf@exceet.de>
      Signed-off-by: Mark Brown <broonie@kernel.org>

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

spi: Import more spi mode defines from Linux ...

Sync with Linux v5.1-rc1.

Define more spi mode flags.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

spi: Generalize SPI "master" to "controller" ...

Sync with Linux v5.1-rc1.

This is the barebox adoption of the commit

  commit 8caab75
  Author: Geert Uytterhoeven <geert+renesas@glider.be>
  Date:   Tue Jun 13 13:23:52 2017 +0200

      spi: Generalize SPI "master" to "controller"

      Now struct spi_master is used for both SPI master and slave controllers,
      it makes sense to rename it to struct spi_controller, and replace
      "master" by "controller" where appropriate.

      For now this conversion is done for SPI core infrastructure only.
      Wrappers are provided for backwards compatibility, until all SPI drivers
      have been converted.

      Noteworthy details:
	- SPI_MASTER_GPIO_SS is retained, as it only makes sense for SPI
	  master controllers,
	- spi_busnum_to_master() is retained, as it looks up masters only,
	- A new field spi_device.controller is added, but spi_device.master is
	  retained for compatibility (both are always initialized by
	  spi_alloc_device()),
	- spi_flash_read() is used by SPI masters only.

      Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
      Signed-off-by: Mark Brown <broonie@kernel.org>

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mtd: spi-nor: cadence: add cqspi_set_protocol ...

Sync up the driver with the original linux v4.7 driver version.

As only Quad-SPI mode is/was supported, the function was not
ported in the initial move to barebox.
To make future synchronizations with the kernel driver easier,
add this function and reorder the functions in the driver
accordingly.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: mvebu: defconfig: update ...

Enable remaining boards and enable some more features.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

arm: add basic support for the Armada XP DB platform ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: rpi3: remove swapped sdhci and sdhost ...

Now that we have a sdhost driver there is no need to swap those
peripherals. As the sdhci peripheral is only used for SDIO, which
isn't supported in Barebox disable it.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: rpi: enable sdhost driver in defconfig ...

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: rpi: add clock for sdhost ...

The sdhost is driven by the core clock.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mci: add driver for BCM283x sdhost core ...

The sdhost is a simple MMC controller found on the Broadcom
BCM283x line of SoCs. The driver code was ported from U-Boot
and then simplified a bit, by dropping a lot of the state
tracking.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: aarch64: do not use 32bit optimized find bit functions ...

The optimized find bit functions are only implemented for 32 bit and are
not built on aarch64 systems. Therefore, for example bootchooser cannot
be build for aarch64.

Select the generic find_bit implementations on aarch64.

As the decision, if lib64 or lib32 is build or not, directly depends on
CPU_V8, the generic implementation also should be used if CPU_V8 is
selected.

Reported-by: Thomas Hämmerle <Thomas.Haemmerle@wolfvision.net>
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

UBI: remove Kconfig entry from include ...

CONFIG_MTD_UBI_WL_THRESHOLD can be set via Kconfig.
default there is also 4096. So remove the leftover here.

Signed-off-by: Jan Remmet <j.remmet@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: zii-imx8mq-dev: select ZII_COMMON ...

The RDU3 shares some of the board fixups with the other Zii boards.
For those to work ZII_COMMON needs to be enabled.

Fixes: d76ba38a1605 (ARM: zii-common: reuse i210 config check for RDU3)
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Documentation: imx: add documentation for RioTboard ...

Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: imx: disable IPU QoS setup for correct SoCs ...

The condition was introduced in 4e6e8f73e9 ("ARM: imx6: don't
execute IPU QoS setup on MX6 SX/SL"), but instead it bails at
the Solo, not the SX and SL.

The original intent was most probably to add an exception for
the i.MX6 Solo as well, so everything else is skipped, including
the SX, SL and now the UL and ULL. Fix the code to reflect this.

On the SX, SL, UL, ULL, this now avoids writes to memory, which
isn't described in the datasheets. On the S, it now configures
the QoS settings.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: vf610: improve handling case that cpu frequency can't be changed ...

Currently we get a nasty error message if the cpu clock can't be
changed:
DDRC is clocked by PLL1, can't switch CPU clockinitcall vf610_switch_cpu_clock+0x1/0x198 failed: Invalid argument

So let's do the following:
- factor out the check from vf610_switch_cpu_clock_to_500mhz() and
  vf610_switch_cpu_clock_to_400mhz
- if clock can't be changed, don't treat it as an error
- don't call clock notifier chain if clock can't be changed
- add trailing newline to the warning message

Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Reviewed-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

fs: nfs: ensure rpc_req message is send ...

Currently we send a rpc message without checking if the send was
succesful and poll for a answer from the server. If the server didn't
answer within the NFS_TIMEOUT window we send the package again. In case
the package send wasn't successful we always run in that timeout. This
gets even worse if the package send fails more than one time.

Check if the package send was successful and resend the package if it
wasn't to fix this behaviour.

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: mmu: mark uncached regions as eXecute never on v7 ...

The ARM Cortex-A Series Programmer's Guide notes[1]:
> When set, the Execute Never (XN) bit in the translation table entry
> prevents speculative instruction fetches taking place from desired
> memory locations and will cause a prefetch abort to occur if execution
> from the memory location is attempted.
>
> Typically device memory regions are marked as execute never to prevent
> accidental execution from such locations, and to prevent undesirable
> side-effects which might be caused by speculative instruction fetches.

Heed the advice and mark uncached memory with the XN bit, when the
CPU is >=v7.

It's possible that there are SoCs that have a section shared between
device memory and the on-chip RAM hosting the PBL.
In such a section, every page except for the OCRAM's should be mapped XN,
but as we know of no SoC with such an OCRAM layout, we ignore this
possibility for now and let mmu_early_enable map sections only.

[1]: 9.6.3 "Execute Never", Version 4.0

Suggested-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: mmu: remove doubly defined macro ...

PMD_SECT_DEF_CACHED is defined along with PMD_SECT_DEF_UNCACHED
in mmu.h, which is included two lines prior.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: cache-armv7: start invalidation from outer levels ...

On 25/4/19 11:57, Lucas Stach wrote:
> [T]he sequence that could go wrong in Barebox is as follows:
> 1. CPU core starts invalidating at L1 cache level
> 2. HW prefetcher decides that a specific address should be brought into
> the L1 cache.
> 3. HW prefetcher finds a valid block for the requested address in L2
> cache and moves cached data from L2 to L1.
> 4. Only now CPU core invalidates L2 cache.
>
> In the above sequence we now have invalid data in the L1 cache line.
> The correct sequence will avoid this issue:
>
> 1. CPU core starts invalidating at L2 cache level
> 2. HW prefetcher decides that a specific address should be brought into
> the L1 cache.
> 3. HW prefetcher sees invalid tags for the requested address in L2
> cache and brings in the data from external memory.
> 4. CPU core invalidates L1 cache, discarding the prefetched data.
>

The ARM Cortex-A Series Programmer's Guide addresses this issue
in the SMP-context[1]:
> If another core were to access the affected address between those
> two actions, a coherency problem can occur. Such problems can be avoided
> by following two simple rules.
>
> * When cleaning, always clean the innermost (L1) cache first and then
>   clean the outer cache(s).
> * When invalidating, always invalidate the outermost cache first and
>   the L1 cache last.

The current code correctly iterates from inner to outer cache levels
when flushing/cleaning (r8 == 0), invalidation (r8 == 1) occurs in the
same direction though. Adjust the invalidation iteration order to start
from the outermost cache instead.

Equivalent C-Code:

	enum cache_op { CACHE_FLUSH = 0, CACHE_INVAL = 1 };
	register enum cache_op operation asm("r8");
	register int i asm("r12");
	register int limit asm("r3") = max_cache_level << 1; // e.g. 4 with L2 max

	+if (operation == CACHE_FLUSH) {
	 	i = 0;
	+} else {
	+	i = limit - 2;
	+}

	 bool loop_again;
	 do {
		/* [snip] */
	+	if (operation == CACHE_FLUSH) {
			i += 2;
			loop_again = limit > i;
	+	} else {
	+		loop_again = i > 0;
	+		i -= 2;
	+	}
	} while (loop_again);

[1]: 18.6 "TLB and cache maintenance broadcast", Version 4.0

Suggested-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: cache-armv7: work around Cortex-A7 erratum 814220 ...

This patch is based on 0e9a87bb from the linux-imx kernel:
------------------------------------------------------------------------------
| ARM/MP: 814220—B-Cache maintenance by set/way operations can execute
| 	out of order.
|
| Description:
| The v7 ARM states that all cache and branch predictor maintenance operations
| that do not specify an address execute, relative to each other, in program
| order. However, because of this erratum, an L2 set/way cache maintenance
| operation can overtake an L1 set/way cache maintenance operation, this would
| cause the data corruption.
|
| This ERRATA affected the Cortex-A7 and present in r0p2, r0p3, r0p4, r0p5.
|
| This patch is the SW workaround by adding a DSB before changing cache levels
| as the ARM ERRATA: ARM/MP: 814220 told in the ARM ERRATA documentation.
| Signed-off-by: Jason Liu <r64343@freescale.com>
------------------------------------------------------------------------------

It was later posted to LKML for Linux inclusion, but is not yet mainline:
<20190214083145.15148-1-benjamin.gaignard@linaro.org>

Unlike the Linux version, we don't make the barrier dependent on a
Kconfig option and always execute the dsb:

On 25/4/19 12:02, Lucas Stach wrote:
> I don't think we need a Kconfig option here. This function is not
> really performance critical. The short pipeline stall introduced by the
> dsb when switching the cache level is minor compared to the time it
> takes to actually move the cache blocks on a clean.
>
> Just always execute the [dsb] and add a comment on why it is needed.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: zii-vf610-dev: Add ZII SSMB DTU board ...

Add the Zodiac Digital Tapping Unit, a VF610 based network device with
5 Ethernet ports.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

doc: clarify state framework driver requirement

ARM: aarch64: lowlevel: Reset SCTLR_EL3 in arm_cpu_lowlevel_init() ...

There's no guarantee that when arm_cpu_lowlevel_init() runs at EL3,
SCTLR will be in a state we expect it to be. Add code to reset it to a
known state, so we'd always start form clean slate. This is also
matches what we've been doing non 64-bit ARMs.

Real word motivation for this patch is i.MX8MQ whose rev 2.1 silicon
appear to have different mask ROM behaviour where it now leaves MMU
enabled if no valid boot source is found. Page table it sets up
doesn't include DDR range, so trying to bootstrap the device via
JTAG/OpenOCD results in an abort.

The value for SCTLR_ELx_FLAGS was taken from Linux kernel.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>