ARM: imx: select OFDEVICE for VF610 ...

It's a dependency for IMX_OCOTP, which is selected by VF610.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: phytec-som-imx6: Add full featured phyCORE-i.MX 6ULL ...

The phyCORE-i.MX 6ULL now comes in a full featured (Y2 variant) and a
low cost (Y0 variant) version. The main difference for the barebox is
the missing second USB OTG port on the Y0 variant and the RAM configuration.

So to account for these differences the existing low cost version is
renamed and the full featured version added.

The results are following phyCORE-i.MX 6ULL modules:

phyCORE-i.MX 6ULL low cost:
	- i.MX 6ULL Y0
	- 256 MB RAM
	- NAND
	- Ethernet 10/100 MBits
	- USB OTG

phyCORE-i.MX 6ULL full featured:
	- i.MX 6ULL Y2
	- 512 MB RAM
	- NAND
	- Ethernet 10/100 MBits
	- USB OTG
	- USB Host

Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: dts: phyCORE-i.MX 6UL/ULL: Enable USB OTG on port 1 ...

Enable USB OTG support on USB OTG port 1 of the phyCORE-i.MX 6UL/ULL.

Signed-off-by: Fabian Godehardt <fg@emlix.com>
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: dts: phyCORE-i.MX 6UL: Enable USB host port ...

The phyBOARD-Segin baseboard of the phyCORE-i.MX 6UL features a USB
type A connector on the second USB OTG port of the i.MX 6UL. So enable this
port as a host port.

Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

nvmem: ocotp: Add support for second mac address fuses on imx6ul ...

The i.MX 6UL/ULL has fuses for two MAC addresses. Both MAC addresses
share the fuse address 0x23.

		-----------------------------
	0x22	| MAC0 | MAC0 | MAC0 | MAC0 |
		-----------------------------
	0x23	| MAC0 | MAC0 | MAC1 | MAC1 |
		-----------------------------
	0x24	| MAC1 | MAC1 | MAC1 | MAC1 |
		-----------------------------

So to read the second MAC address the first two bytes of 0x23 need to be
skipped.

Signed-off-by: Christian Hemp <c.hemp@phytec.de>
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

i.MX: HABv4: always print HAB status at boot time ...

Currently, board code needs to call habv4_get_status() explicitely, but
there is no reason that it cannot be called automatically at startup
when HABv4 is enabled. This way the call cannot be forgotten and we can
make sure to report all potentially occuring HAB warnings and errors.

Signed-off-by: Roland Hieber <r.hieber@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

drivers: caam: add RNG software self-test ...

This patch is based on a vendor patch in U-Boot, taken from
https://portland.source.codeaurora.org/patches/external/imxsupport/uboot-imx/imx_v2016.03_4.1.15_2.0.0_ga/HAB-238-Run-RNG-self-test-for-impacted-i.MX-chips.zip

|    HAB-238 Run RNG self test for impacted i.MX chips
|
|    Patch is only applicable to imx_v2016.03_4.1.15_2.0.0_ga branch of u-boot.
|    Please adapt the patch for your respective release version.
|
|    Background:
|    Few i.MX chips which have HAB 4.2.3 or beyond, have oberserved following
|    warning message generated by HAB due to incorrect implementation of drng
|    self test in boot ROM.
|
|        Event       |0xdb|0x0024|0x42| SRCE Field: 69 30 e1 1d
|                    |    |      |    |             STS = HAB_WARNING (0x69)
|                    |    |      |    |             RSN = HAB_ENG_FAIL (0x30)
|                    |    |      |    |             CTX = HAB_CTX_ENTRY (0xE1)
|                    |    |      |    |             ENG = HAB_ENG_CAAM (0x1D)
|                    |    |      |    | Evt Data (hex):
|                    |    |      |    |  00 08 00 02 40 00 36 06 55 55 00 03 00 00 00 00
|                    |    |      |    |  00 00 00 00 00 00 00 00 00 00 00 01
|
|    It is recommended to run this rng self test before any RNG related crypto
|    implementations are done.
|
[...]
|
|    Signed-off-by: Utkarsh Gupta <utkarsh.gupta@nxp.com>

Currently known impacted chips, as determined by NXP, include:
* i.MX6DQ+ silicon revision 1.1
* i.MX6DQ silicon revision 1.6
* i.MX6DLS silicon revision 1.4
* i.MX6SX silicon revision 1.4
* i.MX6UL silicon revision 1.2
* i.MX67SD silicon revision 1.3

Port the RNG software self-test from this patch to barebox. It can be
enabled by selecting CRYPTO_DEV_FSL_CAAM_RNG_SELF_TEST in Kconfig.

The original patch included a command line utility to run the self-test,
but we choose a different approach here, and run the software self-test
automatically when the respective HAB events indicating a RNG ROM
self-test failure are found when running habv4_get_status(). Note that
habv4_get_status() must be called by the board code before the CAAM
device driver is probed for this mechanism to work.

Until now there are at least two such known events. The first event was
observed on an i.MX6Solo, silicon revision 1.4; the second event is
mentioned in the original patch description given above. When an event
occured, habv4_get_status() tests if it is one of those known events,
and if so, indicates to the CAAM driver to run the software self-test.
In this case, printing the respective HAB warning is suppressed to
prevent confusion; the software self-test itself will error out in case
of recurring RNG self-test failure.

Signed-off-by: Roland Hieber <r.hieber@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: images: use piggydata ...

The way we assemble the multi images on ARM is rather complicated and
error prone. We currently cat the compressed barebox image behind the
PBL executable and need some magic to obtain the size of the payload and
also have to do tricks to reliably get a pointer to the compressed
image.

This patch switches over to compile the compressed payload into the PBL
image itself which has proven to work for the single PBL case and for
the ARM Linux Kernel aswell.

The goal is to unify the single PBL and the multi PBL cases together in
the future to get an easier startup path for ARM.

This patch has been tested on the i.MX53 QSB, i.MX53 Vincell, Beaglebone
black (both MLO and 2nd stage) and a Phytec phyFLEX i.MX6 board.

SoCFPGA Arria10 has also be changed slightly with this patch. We used to
generate a single image (barebox-socfpga-achilles.img) which was
used as xload image and full image. We now instead generate two images:
barebox-socfpga-achilles-xload.img and barebox-socfpga-achilles.img, the
former loaded by the ROM and the latter loaded by the xload image.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX: Add max_load_size option to boards that will need it ...

The max_load_size option makes sure that only the portion of the image
is loaded to SRAM that fits into it.

Note this does not cover the whole available SRAM area for all boards,
for the bigger SRAM areas only a part is chosen that is enough to fit
the initial loader in.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

scripts: imx-image: Add support for max_load_size option ...

When an image is loaded to SRAM we can normally only load a part of the
full image, limited by the available space in SRAM. We currently load
the pblb image which is the executable part of the PBL without the
compressed barebox payload. We are going to link the compressed barebox
image into the pbl image though, so we can't see the desired load size
from outside the image anymore.

This adds a max_load_size option to set this size explicitly.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

scripts: imx-image: Fix typos in comments ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX: GuF Vincell: Make pbl smaller ...

The PBL unnecessarily contains two dtb files when only one is needed. Be
a bit more smart and compile in only one.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX: GuF Vincell: Use DCD table to setup SDRAM ...

This patch removes the xload mechanism to configure SDRAM and instead
installs a DCD table. The DCD table has been generated from the FSL
DDR3 script aid Excel sheet (version 0.0.1). The calibration values
were taken from a calibration run with the barebox internal functions.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

video: ipuv3: use non-fractional clock for parallel display ...

There is no need to keep DI and parent clock in sync for the parallel
display interface, but some displays really don't like the jitter
introduced by using a fractional clock.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

video: ipuv3: use closest fractional divider ...

Currently the divider is always rounded down, which may lead to a
rather big overshoot of the display clock. Try to match the clock
better by rounding to closest.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX5 clock: add clock provider support ...

Currently it is impossible to get clks with clk_get(&clk, "name");
on the mx5 platform. Change that by adding clk-imx5 as clk_provider.

Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: straighten some inline wrappers for use without of support ...

- Move struct clk_onecell_data outside of CONFIG_COMMON_CLK_OF_PROVIDER
- Provide static inline wrapper for of_clk_add_provider()
- Provide static inline wrapper for of_clk_src_onecell_get()

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/usb'

Merge branch 'for-next/state'

Merge branch 'for-next/socfpga'

Merge branch 'for-next/rpi3'

Merge branch 'for-next/net-switch-mv88e6xxx'

Merge branch 'for-next/net'

Merge branch 'for-next/mtd'

Merge branch 'for-next/missing-prototypes'

Merge branch 'for-next/misc'

Merge branch 'for-next/malloc'

Merge branch 'for-next/imx'

Merge branch 'for-next/gpio'

Merge branch 'for-next/dts'