.gitignore: import some updates from Linux ...

[1] sort the normal rule alphabetically again

[2] add leading and trailing slashes to generated directories
   (based on Linux commit 1e35663)

[3] add more Kconfig presets
   (based on Linux commit 7fb1fc4)

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

arch: add KBUILD_DEFCONFIG to allow "make defconfig" ...

Currently, "make defconfig" is only supported for sandbox and x86.

I set KBUILD_DEFCONFIG to support "make defconfig" where I was able
to find a suitable one.

nios2 and openrisc have a single generic_defconfig, so it is definitely
good for KBUILD_DEFCONFIG.

For arm, mips, I assume qemu is a preferred choice over a real board.

blackfin has only one defconfig. Since it is inactive (it is gone in
Linux), so no more defconfig will come in.

I am not sure about ppc and riscv, so I did not touch them.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/ubifs'

Merge branch 'for-next/qspi'

Merge branch 'for-next/ppc'

Merge branch 'for-next/mvebu'

Merge branch 'for-next/mmc'

Merge branch 'for-next/misc'

Merge branch 'for-next/mips'

Merge branch 'for-next/layerscape'

Merge branch 'for-next/imx'

Merge branch 'for-next/dts'

Merge branch 'for-next/ctrlc'

Merge branch 'for-next/blobgen'

Merge branch 'for-next/arm'

dts: update to v5.1 ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

dts: update to v5.1-rc7 ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

dts: update to v5.1-rc6 ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

dts: update to v5.1-rc4 ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Release v2019.05.0 ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Layerscape: Add device tree compatible to image metadata ...

Enrich the image metadata with the device tree compatible string
the image supports.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Layerscape: TQMLS1046a: Add environment and update handlers ...

The TQMLS1046a can boot from QSPI and SD/MMC. Add partitioning for these
devices and barebox environment / barebox update handlers on them.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Layerscape: TQMLS1046a: Support booting from QSPI ...

We have to build correct images suitable for QSPI, thus have to call
lspbl_spi_image instead of lspbl_image. In lowlevel code call the
xload function which detects the bootsource rather than hardcoding
SD/MMC.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Layerscape: TQMLS1046a: unify pbi files ...

This unifies the two different pbi files. With our approach for QSPI
booting differences in the pbi files are not necessary:

- We do not do execute in place for QSPI, so we do not need different
  image execution addresses
- Setting up the QSPI clock doesn't hurt even for SD boot

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Layerscape: TQMLS1046a: print life signs when debugging ...

Do the UART initialization after the SoC specific lowlevel setup and
print the usual '>' when early debuging is enabled. To let this go out
properly it seems we have to wait a small amount of time beforehand.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Layerscape: TQMLS1046a: Sync qspi RCW from TQ U-Boot ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Layerscape: TQMLS1046a: configure qspi divider ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Layerscape: ls1046a: Add bbu handlers ...

The barebox images can simply be written to the partitions, so we can
use bbu_register_std_file_update() for updating to MMC and QSPI.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Layerscape: ls1046a: Add automatic bootsource detection xload function ...

Add a helper function which continues booting from the detected
boot source.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Layerscape: Add QSPI boot support ...

Booting Layerscape from QSPI is a bit tricky and the approach we take is
different from the one U-Boot has taken, so it's worth writing and
reading the following explanation.

The QSPI controller can map the Flash contents into the memory space (On
LS1046a at 0x40000000). The PBL unit uses this to read the RCW from this
memory window. The Layerscape SoCs have a PowerPC history, so it seemed
appropriate for the designers to let the QSPI controller operate in
big endian mode by default. To let the SoC see the correct RCW we have
to write the RCW and PBI data with be64 endianess. Our PBL image tool
pokes the initial binary into the SoC internal SRAM using PBI data as
done with SD/MMC boot aswell. barebox then changes the QSPI controller
endianess to le64 to properly read the barebox binary (placed at an
flash offset of 128KiB, so found in memory at 0x40020000) into SDRAM and
jumps to it.

U-Boot has another approach. Here the initial binary is executed in
place directly at 0x40100000. This means the QSPI controller endianess
must be swapped inside the PBI data. This has the effect that the whole
RCW/PBI data must be 64bit endianess swapped *except* the very last word
of the PBI data which contains the CRC command and is read already with
changed endianess. As a conclusion when porting QSPI PBI files from U-Boot
to barebox skip commands changing the endianess in the QSPI controller
and make sure the image is executed in internal SRAM and not in the
Flash memory window.

Lines like this should be removed:

09550000 000f400c

This sets the binary execution address:

09570604 40100000

For barebox it should be changed to 0x10000000.

As a result the PBI files can probably be unified between SD and QSPI
boot.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>