pinctrl: imx-iomux-v3: Add i.MX8MP compatible ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

serial: i.MX: Add i.MX8MP compatible ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

scripts: imx-image: rename dcdofs to ivtofs ...

This renames the dcdofs config option in the imx-image tool to ivtofs.  dcdofs
is a misnomer. The DCD (Device Configuration Data) is only one part of the data
linked into the IVT (Image Vector Table), but the meaning of the option is
really the latter, not the former.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

scripts: imx-image: rename image_dcd_offset to image_ivt_offset ...

image_dcd_offset is a misnomer, it should really be image_ivt_offset.
The DCD (Device Configuration Data) is only one part of the data linked
into the IVT (Image Vector Table), but the meaning of the variable is
really the latter, not the former.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

scripts: imx-image: Fix writing image with IVT offset = 0 ...

When we have written the barebox header the next thing we do is to lseek
forward by the size of the header gap. This means our position is
already inside of the rest of the image and we have to skip this offset
from the rest of the image. This only works when the rest of the image
doesn't have anything needed in the first few bytes. Some newer SoCs
have the IVT at offset 0 though, so with the current approach we skip
writing the IVT.
Instead of doing this we should lseek to the end of the header gap.
With this we are at the right position to just write the full image
containing the IVT.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

scripts: imx-image: exit with error when barebox header conflicts with IVT ...

When the IVT is right at the beginning of the image it conflicts with
the barebox header. Bail out with an error when this happens.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

scripts: imx-image: Add extra code path for i.MX35 ...

The i.MX35 writes two copies of the header at the beginning of the
image. This is written in a loop right now. Make the i.MX35 an extra
code path so that it is out of the way for the changes in the next
patches.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

scripts: imx-image: exit on read/write failures ...

When xread/xwrite fails the caller bails out of the program with an
error. We can drop all the error handling by letting xread/xwrite
call exit() themselves.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

scripts: imx-image: Only set DCD pointer when we have DCD data ...

When we do not have any DCD data we can set the pointer to the
data to NULL.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

net:fec: fixed unaligned access and stack corruption ...

on 64 bit architectures, the 'enum fec_type' might not be aligned and
large enough to hold a pointer.  When running barebox without MMU,
this will crash like

| i.MX8MM unique ID: dab4b7491a2c4209
| DABT (current EL) exception (ESR 0x96000061) at 0x00000000fffefeb4
| elr: 00000000ffe14c28 lr : 00000000ffe196e0
| x0 : 0000000000000002 x1 : 00000000fffefeb4
| x2 : 00000000ffe91370 x3 : 00000000bfe1b6e8
| x4 : 0000000000000000 x5 : 0000000011000000
| ...
| Call trace:
| [<ffe14c28>] (dev_get_drvdata+0xc/0x30) from [<ffe1446c>] (device_probe+0x54/0xd0)
| [<ffe1446c>] (device_probe+0x54/0xd0) from [<ffe14530>] (match+0x48/0x58)
| [<ffe14530>] (match+0x48/0x58) from [<ffe14a64>] (register_driver+0xc0/0xd0)
| [<ffe14a64>] (register_driver+0xc0/0xd0) from [<ffe01738>] (start_barebox+0x64/0x90)

Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: configs: imx_v7_defconfig: Add bootchooser ...

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Signed-off-by: Robert Karszniewicz <r.karszniewicz@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: configs: imx_v7_defconfig: Add state framework ...

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Signed-off-by: Robert Karszniewicz <r.karszniewicz@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: configs: Update configs to use new Kconfig FASTBOOT_* names ...

Some Kconfig symbols have been moved and renamed in commit
2879373370eb ("fastboot: split generic code from USB gadget")

Signed-off-by: Robert Karszniewicz <r.karszniewicz@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

dts: update to v5.8-rc3 ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mci: omap: add new am335x and am437x SDHCI specific compatibles ...

For a while now, Linux has had a sdhci-omap driver for TI's OMAP SoCs
making use of the SDHCI core library. This was in addition to the
older omap-hsmmc driver, which didn't.

Linux commit 0b4edf11187 ("ARM: dts: Move am33xx and am43xx mmc nodes to
sdhci-omap driver") changes the device tree compatible of the mmc nodes
on the am33xx and am43xx SoCs away from the omap-hsmmc to the SDHCI
driver. Add the new compatibles, so we aren't broken by the change.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: sama5d27-som1: add additional first stage entry point ...

The BootROM constrains us to a 64K big first stage bootloader. Add a PBL
entry point for a xload barebox that sets up the minimum necessary to
load a FAT32 barebox.bin from the SD-Card.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: sama5d2: reduce UART setup boilerplate with new helpers ...

The sama5d2 can be fused for one of 9 preset UART iosets. This is then
used by the BootROM for printing the `RomBOOT' header and for the XMODEM
protocol implemented by the SAM-BA monitor. Add two new sama5d2 specific
helpers:

- sama5d2_dbgu_setup_ll for setting up the port with only pinmux and
  master clock as arguments
- sama5d2_resetup_uart_console for resetup of the uart console with
  same pinmux used by the ROM code

The default value, when unfused, is UART_1_IOSET_1 (RX@PD2, TX@PD3),
which are the same ones used on the two sama5d2 board supported so far.

With this change, the DEBUG_LL baudrate is also no longer fixed at 115200,
but instead comes from the CONFIG_BAUDRATE symbol.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: debug_ll: remove duplicated IS_ENABLED(CONFIG_DEBUG_LL) condition ...

There are three users of at91_dbgu_setup_ll and all already call this
function only when IS_ENABLED(CONFIG_DEBUG_LL). Remove the duplicated
condition from the function itself. This allows us to use the function
for pbl_set_console use later on, even with DEBUG_LL disabled.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: sama5d2: reuse stack set-up by first stage ...

Stack is always set up to end of SRAM before PBL, either by ROM code or
by first stage bootloader, be it at91bootstrap or barebox in a later
commit, so no need to change the stack pointer again.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: add helpers for chain-loading barebox from SD-card ...

With PBL FAT support implemented, provide an sama5d2_sdhci_start_image
helper that can be called from the PBL to chainload a barebox.bin file
from the first FAT partition.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: add code for sama5 boot source detection ...

SAMA5 BootROM passes information about the boot source in the r4
register. Add functions to parse these. To make use of this, entry point
must back up the r4 register, because otherwise it's clobbered by local
variable use.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mci: sdhci: atmel: extend driver for PBL usage ...

The BootROM resets both the SD/MMC host controller and the pin controller,
but the card itself remains in transfer mode. If we redo host-side
setup, we can directly read new blocks off the card.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

fs: fat: extend for in-PBL support ...

The AT91 BootROM loads a boot.bin file from the first FAT partition
into SRAM, when booting from MMC. To avoid the need for two barebox
configurations for each of the bootloader stages, add PBL support
for reading from FAT. This way each stage need only have a different
PBL entry point.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

pbl: add block I/O API ...

We already have some PBL MCI implementations in barebox, but none
are used for chainloading a barebox from a file system.

There are some SoCs that would benefit from this however:
At least the Zynq, AT91, SoCFPGA and TI SoCs.

In preparation for supporting first stage boot on these where it's
customary for both the BootROM and first stage bootloader to load the
follow-up stage from FAT, add a very basic block I/O API that MCI
drivers can implement.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: extend low level PMC driver for generic clk support ...

The SAMA5D2 and SAM9X60 both feature generic clocks, which we already
support in barebox proper, but not in PBL. Add PBL support for setting
the parent and enabling them, so we may use it to enable the SDMMC
peripherals in first stage.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: add necessary Advanced Interrupt Controller configuration ...

Without reconfiguration of the AIC redirection, the OS interrupt
handling will misbehave later on. Add it to the SoC init.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: add sama5d2 cache init ...

The L2 cache controller needs some initialization before use. Same goes
for the CAN SRAM, do so after the MMU setup.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: sama5d2: add sama5d2 matrix configuration ...

Different peripherals, including the SDRAM, are unusable without prior
matrix configuration. Port over the necessary at91bootstrap parts for
sama5d2 use.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: implement sama5d2 lowlevel init ...

Port over the low level initialization for sama5d2 SoCs from
at91bootstrap.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

watchdog: add support for at91sam9/sama5 watchdog ...

The watchdog on these SoCs is enabled by default on system boot, so a
driver is especially useful. According to data sheet the mode register
containing the timeout can be configured only once, but I couldn't
verify this on the sama5d2. Regardless, the driver takes care not to
change the mode register unless necessary. Implementation that want to
leave to the OS the decision which timeout to choose, can just keep
pinging with the POR-default of 16 seconds and the OS will be able to
set the final timeout.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>