ARM: i.MX: HAB: fix missing include for EPERM ...

Signed-off-by: Roland Hieber <r.hieber@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mci: imx-esdhc: send required clock pulses to card on init ...

MMC cards need at least 74 clock pulses before any bus communication
can occur. The i.MX SDHC controller auto-gates the clock when inactive,
so if the SD enumeration is skipped for slots where we know that only a
MMC card can be present (which is possible since
b5289b742a89 "mmc: allow skipping SD card initialization") those
inititialization clock pulses won't be sent out, resulting in command
timeouts when trying to enumerate the card.

Luckily the eSDHC controller has a hardware feature to send out 80
clock pulses. This has been validated to be available by checking the
reference manual back to i.MX25.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

firmware: Fix copy-paste comment mistake ...

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: nxp-imx8mq-evk: Add bootflow comments ...

Add some notes on how the boot-flow goes while I still remember it.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX8MQ: Query and display ATF fimware hash if available ...

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: nxp-imx8mq-evk: Add code to load ATF BL31 blob ...

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX: xload-esdhc: Allow placing image to align its entry point ...

Allow placing image to align its entry point with a particular entry
point address. This is needed for SoC's like i.MX8M where
vendor-provided ARM Trusted Firmware blob will exit at specific
pre-determined address and we need to be able to pick execution up
from there.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX: xload-esdhc: Make use of <mach/imx-header.h> ...

Convert esdhc_start_image() to use constants and data types from
<mach/imx-header.h>. Also, while at it, define a simple inline
function to test if an arbitrary binary blob is i.MX flash header v2.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX: Move i.MX header definitions to mach-imx ...

Move i.MX header definitions from scripts to mach-imx in order to make
it available to both script and bootloader code.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Mark SP as being clobbered in arm_setup_stack() ...

Not sure why it was working before, but with recent update of AArch64
GCC to 8.1.1 on my Fedora 28 machine, compiling barebox_arm_entry()
yields the following assembly:

0000000000002aac <barebox_arm_entry>:
    2aac:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
    2ab0:	d1404023 	sub	x3, x1, #0x10, lsl #12
    2ab4:	d1004063 	sub	x3, x3, #0x10
    2ab8:	910003fd 	mov	x29, sp
    2abc:	8b000063 	add	x3, x3, x0
    2ac0:	a90153f3 	stp	x19, x20, [sp, #16]
    2ac4:	aa0003f3 	mov	x19, x0
    2ac8:	aa0103f4 	mov	x20, x1
    2acc:	f90017e2 	str	x2, [sp, #40] <-- storing 'boarddata' on old stack
    2ad0:	9100007f 	mov	sp, x3 <-- setting up new stack
    2ad4:	97ffffdd 	bl	2a48 <arm_early_mmu_cache_invalidate>
    2ad8:	f94017e2 	ldr	x2, [sp, #40] <--- sadness
    2adc:	aa1403e1 	mov	x1, x20
    2ae0:	aa1303e0 	mov	x0, x19
    2ae4:	940000a1 	bl	2d68 <barebox_multi_pbl_start>

Which result in AArch64 image (i.MX8MQ) not being bootable. With SP
marked as clobbered, the above assembly changes to the following:

0000000000002aac <barebox_arm_entry>:
    2aac:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
    2ab0:	d1404023 	sub	x3, x1, #0x10, lsl #12
    2ab4:	d1004063 	sub	x3, x3, #0x10
    2ab8:	910003fd 	mov	x29, sp
    2abc:	a90153f3 	stp	x19, x20, [sp, #16]
    2ac0:	8b000063 	add	x3, x3, x0
    2ac4:	aa0003f3 	mov	x19, x0
    2ac8:	aa0103f4 	mov	x20, x1
    2acc:	f90017a2 	str	x2, [x29, #40]
    2ad0:	9100007f 	mov	sp, x3
    2ad4:	97ffffdd 	bl	2a48 <arm_early_mmu_cache_invalidate>
    2ad8:	f94017a2 	ldr	x2, [x29, #40]
    2adc:	aa1403e1 	mov	x1, x20
    2ae0:	aa1303e0 	mov	x0, x19
    2ae4:	940000a1 	bl	2d68 <barebox_multi_pbl_start>

now x29 is used to access stored x2 which avoids the problem and
allows the system to boot correctly.

The change is a no-op on AArch32.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: phytec-som-am335x: make autoenable actually usable ...

IS_ENABLED has to be passed the full symbol name including the CONFIG_
prefix. Otherwise IS_ENABLED evaluates to 0.

Fixes: 2877e08f9e1a ("ARM: phytec-som-am335x: Add autoenable")
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
--
Cc: Daniel Schultz <d.schultz@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

usb: gadget: allow to actually enable sparse fastboot support ...

When sparse support was (intended to be) made optional it was
effectively unconditionally disabled because

	IS_ENABLED(USB_GADGET_FASTBOOT_SPARSE)

always evaluates to 0. To actually make use of the introduced kconfig
symbol the CONFIG_ prefix must not be skipped.

Fixes: f4b5d3eeb607 ("usb: gadget: fastboot: Make sparse support optional")
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Tested-by: Gavin Schenk <g.schenk@eckelmann.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mci: s3c: fix providing info callback ...

There is no symbol iCONFIG_MCI_INFO, CONFIG_MCI_INFO makes sense here
and matches what was added in the same commit to other drivers.

Fixes: 73b0d228e5b0 ("driver: Attach info callback to device, not to driver")
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

of_node: clarify help text and do stricter commandline parsing ...

To create an oftree node /path/node I tried after reading the help text
of of_node:

	of_node -c /path node

similar to the syntax of of_property. This didnt result in any output
but still failed to do what I meant.

So clarify the help text to not suggest there are two parameters and
return an usage error if still two (or more) names are passed.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: imx6: gw54xx: add fixup for PCIe switch ...

After the PCIe switch has been scanned its GPIOs need to be
configured as output-high to release the devices behind the
switch from their reset state and make them discoverable to
the bus scan.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

pci: add quirk infrastructure ...

This is a cut down version of the Linux kernel PCI quirk infrastructure,
which allows to register and execute some fixups before the driver is
loaded.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: link PCI devices with potentially existing OF nodes ...

The document "PCI Bus Binding to: IEEE Std 1275-1994 Standard for Boot
(Initialization Configuration) Firmware" describes how the PCI topology
can be described in the DT, in order to augment the PCI devices with
additional information via DT properties.

This patch links OF nodes to the corresponding PCI devices if they
exist, allowing PCI device drivers to query DT information like any
platform device.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: socfpga: achilles: move environment to raw partition ...

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: arria10: update defconfig ...

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: socfpga: achilles: convert to PBL barebox ...

Previously the FPGA was configured externally on the Achilles. On newer versions
this is changed and barebox has to configure the FPGA before the SDRAM can be
used.

If the FPGA is configured via JTAG or from an external memory, the *-bringup
version can be used.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: socfpga: Arria10: support programming FPGA in PBL ...

Some Arria10 boards don't have the FPGA programmed externally.
Instead barebox needs to do that. As the Arria10 has the SDRAM
controller in the FPGA, the first thing we need to do is,
configure the FPGA before the SDRAM can even be used.

It works like this:
  1. boot ROM fetches the PBL from MMC
  2. read the MBR from MMC (this depends on the setup done by the boot ROM)
  3. read the Bitstream from the MMC and program the FPGA
  4. re-read the barebox image from MMC, this time with the full barebox
     that is appended to the PBL
  5. jump into the full barebox

Only supported boot device is eMMC.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: socfpga: arria10-reset-manager: don't reset bootsource ...

Arria10 init code resets all peripherals. Convert this to keep the bootmedium
out of reset and keep the setup done by the boot ROM.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

scripts: socfpga_mkimage: add size feature for PBL barebox ...

Add the switch 's' to fixup the image size into the barebox header.
This is used by the Arria10 PBL code to know the complete image size.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: dts: socfpga: Fix achilles dtc warnings ...

The newer dtc has stricter checks on devicetrees. Fix the warnings.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: socfpga: achilles: update handoff files ...

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: socfpga: arria10: fix SDMMC phase shift ...

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: socfpga: arria10: set default TEXTBASE ...

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: socfpga: arria10-init: split pinsetup ...

Move the setup of the shared- and fpgapins to its own function.
These pins can only be configured and let out of reset after the FPGA has been
programmed.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: socfpga: add SMP_TWD_ADDR for Arria10 ...

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: socfpga: arria10: add ocram base address ...

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>