2019-05-10 |
ARM: Layerscape: TQMLS1046a: unify pbi files
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This unifies the two different pbi files. With our approach for QSPI
booting differences in the pbi files are not necessary:
- We do not do execute in place for QSPI, so we do not need different
image execution addresses
- Setting up the QSPI clock doesn't hurt even for SD boot
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Sascha Hauer
committed
on 10 May 2019
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ARM: Layerscape: TQMLS1046a: print life signs when debugging
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Do the UART initialization after the SoC specific lowlevel setup and
print the usual '>' when early debuging is enabled. To let this go out
properly it seems we have to wait a small amount of time beforehand.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Sascha Hauer
committed
on 10 May 2019
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ARM: Layerscape: TQMLS1046a: Sync qspi RCW from TQ U-Boot
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Sascha Hauer
committed
on 10 May 2019
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ARM: Layerscape: TQMLS1046a: configure qspi divider
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Sascha Hauer
committed
on 10 May 2019
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ARM: Layerscape: ls1046a: Add bbu handlers
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The barebox images can simply be written to the partitions, so we can
use bbu_register_std_file_update() for updating to MMC and QSPI.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Sascha Hauer
committed
on 10 May 2019
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ARM: Layerscape: ls1046a: Add automatic bootsource detection xload function
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Add a helper function which continues booting from the detected
boot source.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Sascha Hauer
committed
on 10 May 2019
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ARM: Layerscape: Add QSPI boot support
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Booting Layerscape from QSPI is a bit tricky and the approach we take is
different from the one U-Boot has taken, so it's worth writing and
reading the following explanation.
The QSPI controller can map the Flash contents into the memory space (On
LS1046a at 0x40000000). The PBL unit uses this to read the RCW from this
memory window. The Layerscape SoCs have a PowerPC history, so it seemed
appropriate for the designers to let the QSPI controller operate in
big endian mode by default. To let the SoC see the correct RCW we have
to write the RCW and PBI data with be64 endianess. Our PBL image tool
pokes the initial binary into the SoC internal SRAM using PBI data as
done with SD/MMC boot aswell. barebox then changes the QSPI controller
endianess to le64 to properly read the barebox binary (placed at an
flash offset of 128KiB, so found in memory at 0x40020000) into SDRAM and
jumps to it.
U-Boot has another approach. Here the initial binary is executed in
place directly at 0x40100000. This means the QSPI controller endianess
must be swapped inside the PBI data. This has the effect that the whole
RCW/PBI data must be 64bit endianess swapped *except* the very last word
of the PBI data which contains the CRC command and is read already with
changed endianess. As a conclusion when porting QSPI PBI files from U-Boot
to barebox skip commands changing the endianess in the QSPI controller
and make sure the image is executed in internal SRAM and not in the
Flash memory window.
Lines like this should be removed:
09550000 000f400c
This sets the binary execution address:
09570604 40100000
For barebox it should be changed to 0x10000000.
As a result the PBI files can probably be unified between SD and QSPI
boot.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Sascha Hauer
committed
on 10 May 2019
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ARM: Layerscape: pblimage: Drop pbl end command
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The PBL image tool includes two commands into the image. These are executed
after the initial image has been uploaded but before the final CRC
check. These commands are "flush" and "wait". According to the reference
manual a "flush" command can be used to read back the the value just
written to CCSR register space in order to let the previous write
complete. This seems unnecessary as the last write was never to the CCSR
register space. The "wait" command also seems unnecessary as the time
parameter is 0. As all this end_cmd stuff goes back to the PowerPC times
and everything still seems to work on Arm let's just remove it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Sascha Hauer
committed
on 10 May 2019
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ARM: Layerscape: ls1046a: Add bootsource detection support
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Not much to do, there are only a few boot sources supported.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Sascha Hauer
committed
on 10 May 2019
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esdhc-xload: invalidate icache before jumping to image
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Sascha Hauer
committed
on 10 May 2019
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bbu: In bbu_register_std_file_update detect device before accessing it
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The device the standard file update handler writes to may not be present
before detecting it, so as a first step detect it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Sascha Hauer
committed
on 10 May 2019
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bbu: bbu_register_std_file_update should take const char*
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String arguments to bbu_register_std_file_update should be const.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Sascha Hauer
committed
on 10 May 2019
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2019-05-09 |
commands/hwclock: align -n option help
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Help string for hwclock -n option isn't aligned:
barebox@barebox sandbox:/ help hwclock
hwclock - query or set the hardware clock (RTC)
Options:
-f NAME RTC device name (default rtc0)
-e VARNAME store RTC readout into variable VARNAME
-n NTPSERVER set RTC from NTP server
-s ccyymmddHHMM[.SS] set time
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Antony Pavlov
authored
on 9 May 2019
Sascha Hauer
committed
on 9 May 2019
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ARM: Layerscape: defconfig: Enable more features
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The TQMLS1046a has an i2c mux and a i2c gpio expander. Add support for
it and also disable early debugging as these are for a single board
only.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Sascha Hauer
committed
on 9 May 2019
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net: fsl-fman: Sync rx buffers for device initially
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The rx buffers must be given to the device initially to work properly.
Otherwise the first packets are corrupted.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Sascha Hauer
committed
on 9 May 2019
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filetype: Detect Layerscape PBL images
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The Layerscape SoCs have their own boot image format. Add filetype
detection for it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Sascha Hauer
committed
on 9 May 2019
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crypto: digest: fix digesting file windows
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When digesting a file we always try toread PAGE_SIZE bytes. When we get a
short read because we reached the file end then the code works
correctly. If instead we only want to digest a part of the file then
we must make sure to only read up to 'size' bytes.
Fixes: b77582effd ("crypto: digest: Split memory vs. file code into separate functions")
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Sascha Hauer
committed
on 9 May 2019
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2019-05-08 |
mtd: spi-nor: Add support for more Macronix devices
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Add support for the Macronix mx66u51235f, mx66l1g45g and mx66l1g55g.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Sascha Hauer
committed
on 8 May 2019
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owc: remove references to GE.
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As per contactual requirement, remove references to GE in the
code.
Signed-off-by: Renaud Barbier <renaud.barbier@abaco.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Barbier, Renaud
authored
on 15 Apr 2019
Sascha Hauer
committed
on 8 May 2019
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owc: directories and files renaming
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As the company changed name to Abaco Systems Inc, we have
a contractual requirement to remove GE references. Start by
renaming files and directories using a neutral name.
Signed-off-by: Renaud Barbier <renaud.barbier@abaco.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Barbier, Renaud
authored
on 15 Apr 2019
Sascha Hauer
committed
on 8 May 2019
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ARM: Layerscape: TQMLS1046a: Fix pinmux setup for i2c4
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With this the I2C mux on i2c4 works properly.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Sascha Hauer
committed
on 8 May 2019
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ARM: Layerscape: TQMLS1046a: Unify SD and eMMC images
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TQ has unified SD and eMMC images in their U-Boot. Do the same in
barebox aswell.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Sascha Hauer
committed
on 8 May 2019
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ARM: Layerscape: TQMLS1046a: Update device tree files from tq repository
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Update TQMLS1046a device tree files from TQ repository as of rocko.TQMLS1046A.BSP.SW.0002
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Sascha Hauer
committed
on 8 May 2019
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ARM: Layerscape: TQMLS1046a: Use static DDR settings
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TQ prefers static values in their U-Boot, so use these values in
barebox aswell.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Sascha Hauer
committed
on 8 May 2019
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ddr: fsl: move fsl_ddr_set_memctl_regs prototype to include/
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fsl_ddr_set_memctl_regs() is not only used internally in the DDR
controller driver, but can also be called by the boards to configure
a static setting. Move the prototype to include/ where it can be
used by board code.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Sascha Hauer
committed
on 8 May 2019
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ARM: Layerscape: TQMLS1046a: Set cpo_sample value
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Starting the board issues the warning:
WARN: pls set popts->cpo_sample = 0x48
So set the value to the desired value.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Sascha Hauer
committed
on 8 May 2019
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mci: imx-esdhc-pbl: ls1046a: Set better divider values
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MMC Frequency was set to something like 55MHz. This doesn't work for all
SD cards. Set to 25MHz which is supported by all SD cards.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Sascha Hauer
committed
on 8 May 2019
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mtd: devices: m25p80: use the spi_mem_xx() API
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This is the barebox adoption of the linux v4.16 patch
4120f8d
Author: Boris Brezillon <bbrezillon@kernel.org>
AuthorDate: Thu Apr 26 18:18:19 2018 +0200
Commit: Mark Brown <broonie@kernel.org>
CommitDate: Fri May 11 11:33:51 2018 +0900
mtd: spi-nor: Use the spi_mem_xx() API
The spi_mem_xxx() API has been introduced to replace the
spi_flash_read() one. Make use of it so we can get rid of
spi_flash_read().
Note that using spi_mem_xx() also simplifies the code because this API
takes care of using the regular spi_sync() interface when the optimized
->mem_ops interface is not implemented by the controller.
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@exceet.de>
Tested-by: Frieder Schrempf <frieder.schrempf@exceet.de>
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Steffen Trumtrar
authored
on 3 May 2019
Sascha Hauer
committed
on 8 May 2019
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mtd: spi-nor: provide default erase_sector implementation
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Based on the Linux v4.4 patch
commit c67cbb8
Author: Brian Norris <computersforpeace@gmail.com>
AuthorDate: Tue Nov 10 12:15:27 2015 -0800
Commit: Brian Norris <computersforpeace@gmail.com>
CommitDate: Thu Nov 19 13:34:44 2015 -0800
mtd: spi-nor: provide default erase_sector implementation
Some spi-nor drivers perform sector erase by duplicating their
write_reg() command. Let's not require that the driver fill this out,
and provide a default instead.
Tested on m25p80.c and Medatek's MT8173 SPI NOR flash driver.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Steffen Trumtrar
authored
on 3 May 2019
Sascha Hauer
committed
on 8 May 2019
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mtd: spi-nor: introduce SPI 1-2-2 and SPI 1-4-4 protocols
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Sync the driver with Linux v4.12 and apply the patch
commit cfc5604
Author: Cyrille Pitchen <cyrille.pitchen@atmel.com>
AuthorDate: Tue Apr 25 22:08:46 2017 +0200
Commit: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
CommitDate: Mon May 15 21:56:17 2017 +0200
mtd: spi-nor: introduce SPI 1-2-2 and SPI 1-4-4 protocols
This patch changes the prototype of spi_nor_scan(): its 3rd parameter
is replaced by a 'struct spi_nor_hwcaps' pointer, which tells the spi-nor
framework about the actual hardware capabilities supported by the SPI
controller and its driver.
Besides, this patch also introduces a new 'struct spi_nor_flash_parameter'
telling the spi-nor framework about the hardware capabilities supported by
the SPI flash memory and the associated settings required to use those
hardware caps.
Then, to improve the readability of spi_nor_scan(), the discovery of the
memory settings and the memory initialization are now split into two
dedicated functions.
1 - spi_nor_init_params()
The spi_nor_init_params() function is responsible for initializing the
'struct spi_nor_flash_parameter'. Currently this structure is filled with
legacy values but further patches will allow to override some parameter
values dynamically, for instance by reading the JESD216 Serial Flash
Discoverable Parameter (SFDP) tables from the SPI memory.
The spi_nor_init_params() function only deals with the hardware
capabilities of the SPI flash memory: especially it doesn't care about
the hardware capabilities supported by the SPI controller.
2 - spi_nor_setup()
The second function is called once the 'struct spi_nor_flash_parameter'
has been initialized by spi_nor_init_params().
With both 'struct spi_nor_flash_parameter' and 'struct spi_nor_hwcaps',
the new argument of spi_nor_scan(), spi_nor_setup() computes the best
match between hardware caps supported by both the (Q)SPI memory and
controller hence selecting the relevant settings for (Fast) Read and Page
Program operations.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Steffen Trumtrar
authored
on 3 May 2019
Sascha Hauer
committed
on 8 May 2019
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