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2020-01-24	dc2d366 Browse files » intel: Unify Platform specific defines for PSCI module ... PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: Id3d3efc7e7711d19f0223da823713b8390ad2f47 Deepika Bhavnani authored on 13 Dec 2019 Soby Mathew committed on 24 Jan 2020
	076d897 Browse files » Merge "marvell: Unify Platform specific defines for PSCI module" into integration Soby Mathew authored on 24 Jan 2020 TrustedFirmware Code Review committed on 24 Jan 2020
	ac2f6d4 Browse files » marvell: Unify Platform specific defines for PSCI module ... PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: I7d660d5a9d7e44601353c77e9b6ee4096a277d76 Deepika Bhavnani authored on 13 Dec 2019 Soby Mathew committed on 24 Jan 2020
	713403c Browse files » Merge "rockchip: Unify Platform specific defines for PSCI module" into integration Soby Mathew authored on 24 Jan 2020 TrustedFirmware Code Review committed on 24 Jan 2020
	ed7a563 Browse files » rockchip: Unify Platform specific defines for PSCI module ... PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: I624c15d569db477506a74964bc828e1a932181d4 Deepika Bhavnani authored on 13 Dec 2019 Soby Mathew committed on 24 Jan 2020
	133e6f7 Browse files » Merge "allwinner: Unify Platform specific defines for PSCI module" into integration Soby Mathew authored on 24 Jan 2020 TrustedFirmware Code Review committed on 24 Jan 2020
	e0b4cc7 Browse files » allwinner: Unify Platform specific defines for PSCI module ... PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: I7aea86891e54522c88af5ff16795a575f9a9322d Deepika Bhavnani authored on 13 Dec 2019 Soby Mathew committed on 24 Jan 2020
	22d7dd7 Browse files » Merge "imx: Unify Platform specific defines for PSCI module" into integration Soby Mathew authored on 24 Jan 2020 TrustedFirmware Code Review committed on 24 Jan 2020
	7a57188 Browse files » imx: Unify Platform specific defines for PSCI module ... PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: I8b19e833a4e1067e1cfcc9bfaede7854e0e63004 Deepika Bhavnani authored on 13 Dec 2019 Soby Mathew committed on 24 Jan 2020
	7adb7a8 Browse files » Merge "hisilicon: Unify Platform specific defines for PSCI module" into integration Soby Mathew authored on 24 Jan 2020 TrustedFirmware Code Review committed on 24 Jan 2020
	28abb2c Browse files » hisilicon: Unify Platform specific defines for PSCI module ... PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: I327a8a2ab0f0e49bd62f413296c3b326393422b6 Deepika Bhavnani authored on 13 Dec 2019 Soby Mathew committed on 24 Jan 2020
	90b686c Browse files » Merge changes from topic "tegra-downstream-01202020" into integration ... * changes: Tegra194: mce: remove unused NVG functions Tegra194: support for NVG interface v6.6 Tegra194: smmu: add PCIE0R1 mc reg to system suspend save list Tegra194: enable driver for general purpose DMA engine Tegra194: access XUSB_PADCTL registers on Si/FPGA platforms Tegra194: organize the memory/mmio map to make it linear Tegra194: memctrl: enable mc sid OVERRIDE for PCIE0R1 Tegra194: support for boot params wider than 32-bits Tegra194: memctrl: set reorder depth limit for PCIE blocks Tegra194: memctrl: program MC_TXN_OVERRIDE reg for PTCR, MPCORE and MIU Tegra194: memctrl: set CGID_TAG_ADR instead of CGID_TAG_DEFAULT Tegra194: memctrl: update mss reprogramming as HW PROD settings Tegra194: memctrl: Disable PVARDC coalescer Tegra194: memctrl: force seswr/rd transactions as passsthru & coherent Tegra194: Request CG7 from last core in cluster Tegra194: toggle SE clock during context save/restore Tegra: bpmp: fix header file paths Soby Mathew authored on 24 Jan 2020 TrustedFirmware Code Review committed on 24 Jan 2020
	064d3f6 Browse files » Merge "xlat_tables_v2: simplify end address checks in mmap_add_region_check()" into integration Soby Mathew authored on 24 Jan 2020 TrustedFirmware Code Review committed on 24 Jan 2020
	5f3ed6a Browse files » Merge "Prevent speculative execution past ERET" into integration Soby Mathew authored on 24 Jan 2020 TrustedFirmware Code Review committed on 24 Jan 2020
	4e1b0b1 Browse files » Merge "Xilinx zynqmp: add missing pin control group for ethernet 0." into integration Manish Pandey authored on 24 Jan 2020 TrustedFirmware Code Review committed on 24 Jan 2020
2020-01-23	b253407 Browse files » Merge changes from topic "bridge-en" into integration ... * changes: intel: Add function to check fpga readiness intel: Add bridge control for FPGA reconfig intel: FPGA config_isdone() status query intel: System Manager refactoring intel: Refactor reset manager driver intel: Enable bridge access in Intel platform intel: Modify non secure access function Manish Pandey authored on 23 Jan 2020 TrustedFirmware Code Review committed on 23 Jan 2020
	208ebe7 Browse files » Merge "xilinx: versal: PLM to ATF handover" into integration Alexei Fedorov authored on 23 Jan 2020 TrustedFirmware Code Review committed on 23 Jan 2020
	744a1d6 Browse files » Merge "xilinx: common: Move ATF handover to common file" into integration Alexei Fedorov authored on 23 Jan 2020 TrustedFirmware Code Review committed on 23 Jan 2020
	532df95 Browse files » Tegra194: mce: remove unused NVG functions ... This patch removes unused functions from the NVG driver. * nvg_enable_power_perf_mode * nvg_disable_power_perf_mode * nvg_enable_power_saver_modes * nvg_disable_power_saver_modes * nvg_roc_clean_cache * nvg_roc_flush_cache Change-Id: I0387a40dec35686deaad623a8350de89acfe9393 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Varun Wadekar committed on 23 Jan 2020
	54990e3 Browse files » Tegra194: support for NVG interface v6.6 ... This patch updates the NVG interface header file to v6.6. Change-Id: I2f5df274bf820ba1c5df47d8dcbf7f5f056ff45f Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Varun Wadekar committed on 23 Jan 2020
	844e6cc Browse files » Tegra194: smmu: add PCIE0R1 mc reg to system suspend save list ... PCIE0R1 security and override registers need to be preserved across system suspend. Adding them to system suspend save register list. Due to addition of above registers, increasing context save memory by 2 bytes. Change-Id: I1b3a56aee31f3c11e3edc2fb0a6da146eec1a30d Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Pritesh Raithatha authored on 19 Apr 2018 Varun Wadekar committed on 23 Jan 2020
	4a9026d Browse files » Tegra194: enable driver for general purpose DMA engine ... This patch enables the GPCDMA for all Tegra194 platforms to help accelerate all the memory copy operations. Change-Id: I8cbec99be6ebe4da74221245668b321ba9693479 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Varun Wadekar committed on 23 Jan 2020
	db891f3 Browse files » Tegra194: access XUSB_PADCTL registers on Si/FPGA platforms ... Many simulation/emulation platforms do not support this hardware block leading to SErrors during register accesses. This patch conditionally accesses the registers from this block only on actual Si and FPGA platforms. Change-Id: Ic22817a8c9f81978ba88c5362bfd734a0040d35d Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Varun Wadekar committed on 23 Jan 2020
	ceb1202 Browse files » Tegra194: organize the memory/mmio map to make it linear ... This patch organizes the platform memory/mmio map, so that the base addresses for the apertures line up in ascending order. This makes it easier for the xlat_tables_v2 library to create mappings for each mmap_add_region call. Change-Id: Ie1938ba043820625c9fea904009a3d2ccd29f7b3 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Varun Wadekar committed on 23 Jan 2020
	939fd3d Browse files » Tegra194: memctrl: enable mc sid OVERRIDE for PCIE0R1 ... PCIE0R1 does not program stream IDs, so allow the stream ID to be overriden by the MC. Change-Id: I4dbd71e1ce24b11e646de421ef68c762818c2667 Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Pritesh Raithatha authored on 8 Mar 2018 Varun Wadekar committed on 23 Jan 2020
	33a8ba6 Browse files » Tegra194: support for boot params wider than 32-bits ... The previous bootloader is not able to pass boot params wider than 32-bits due to an oversight in the scratch register being used. A new secure scratch register #75 has been assigned to pass the higher bits. This patch adds support to parse the higher bits from scratch #75 and use them in calculating the base address for the location of the boot params. Scratch #75 format ==================== 31:16 - bl31_plat_params high address 15:0 - bl31_params high address Change-Id: Id53c45f70a9cb370c776ed7c82ad3f2258576a80 Signed-off-by: Steven Kao <skao@nvidia.com> Steven Kao authored on 9 Feb 2018 Varun Wadekar committed on 23 Jan 2020
	34a6610 Browse files » Tegra194: memctrl: set reorder depth limit for PCIE blocks ... HW bug in third party PCIE IP - PCIE datapath hangs when there are more than 28 outstanding requests on data backbone for x1 controller. Suggested SW WAR is to limit reorder_depth_limit to 16 for PCIE 1W/2AW/3W clients. Change-Id: Id5448251c35d2a93f66a8b5835ae4044f5cef067 Signed-off-by: Puneet Saxena <puneets@nvidia.com> Puneet Saxena authored on 7 Mar 2018 Varun Wadekar committed on 23 Jan 2020
	eb41fee Browse files » Tegra194: memctrl: program MC_TXN_OVERRIDE reg for PTCR, MPCORE and MIU ... -PTCR is ISO client so setting it to FORCE_NON_COHERENT. -MPCORER, MPCOREW and MIU0R/W to MIU7R/W clients itself will provide ordering so no need to override from mc. -MIU0R/W to MIU7R/W clients registers are not implemented in tegrasim so skipping it for simulation. -All the clients need to set CGID_TAG_ADR to maintain request ordering within a 4K boundary. Change-Id: Iaa3189a1f3e40fb4cef28be36bc4baeb5ac8f9ca Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Pritesh Raithatha authored on 1 Mar 2018 Varun Wadekar committed on 23 Jan 2020
	90dce0f Browse files » Tegra194: memctrl: set CGID_TAG_ADR instead of CGID_TAG_DEFAULT ... - All SoC clients should use CGID_TAG_ADR to improve perf - Remove tegra194_txn_override_cfgs array that is not getting used. Change-Id: I9130ef5ae8659ed5f9d843ab9a0ecf58b5ce9c74 Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Pritesh Raithatha authored on 8 Feb 2018 Varun Wadekar committed on 23 Jan 2020
	1296da6 Browse files » Tegra194: memctrl: update mss reprogramming as HW PROD settings ... Memory clients are divided in to ISO/NonISO/Order/Unordered/Low BW/High BW. Based on the client types, HW team recommends, different memory ordering settings, IO coherency settings and SMMU register settings for optimized performance of the MC clients. For example ordered ISO clients should be set as strongly ordered and should bypass SCF and directly access MC hence set as FORCE_NON_COHERENT. Like this there are multiple recommendations for all of the MC clients. This change sets all these MC registers as per HW spec file. Change-Id: I8a8a0887cd86bf6fe8ac7835df6c888855738cd9 Signed-off-by: Puneet Saxena <puneets@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Puneet Saxena authored on 5 Jan 2018 Varun Wadekar committed on 23 Jan 2020