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History for arm-trusted-firmware / plat / intel / soc / agilex

2020-06-08	e734ecd Browse files » plat: intel: Add FPGAINTF configuration to when configuring pinmux ... FPGAINTF wasn't enabled when configuring pinmux. This fixes the issue. Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com> Change-Id: I5a6aacd504901b8f7327b2f4854b8a77d0c37019 Tien Hock Loh authored on 11 May 2020 Manish Pandey committed on 8 Jun 2020
	aea772d Browse files » plat: intel: set DRVSEL and SMPLSEL for DWMMC ... DRVSEL and SMPLSEL needs to be set so that it can properly go into full speed mode. This needs to be done in EL3 as the registers are secured. Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com> Change-Id: Ia2f348e7742ff7b76da74d392ef1ce71e2f41677 Tien Hock Loh authored on 11 May 2020 Manish Pandey committed on 8 Jun 2020
	fa09d54 Browse files » plat: intel: Fix clock configuration bugs ... This fixes a few issues on the Agilex clock configuration: - Set clock manager into boot mode before configuring clock - Fix wrong divisor used when calculating vcocalib - PLL sync configuration should be read and then written - Wait PLL lock after PLL sync configuration is done - Clear interrupt bits instead of set interrupt bits after configuration Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com> Change-Id: I54c1dc5fe9b102e3bbc1237a92d8471173b8af70 Tien Hock Loh authored on 11 May 2020 Manish Pandey committed on 8 Jun 2020
2020-02-28	351d358 Browse files » Merge "intel: Enable EMAC PHY in Intel FPGA platform" into integration Sandrine Bailleux authored on 28 Feb 2020 TrustedFirmware Code Review committed on 28 Feb 2020
2020-02-25	98964f0 Browse files » 16550: Use generic console_t data structure ... Since now the generic console_t structure holds the UART base address as well, let's use that generic location and drop the UART driver specific data structure at all. Change-Id: I5c2fe3b6a667acf80c808cfec4a64059a2c9c25f Signed-off-by: Andre Przywara <andre.przywara@arm.com> Andre Przywara committed on 25 Feb 2020
2020-02-24	d603fd3 Browse files » intel: Enable EMAC PHY in Intel FPGA platform ... This initializes the EMAC PHY in both Stratix 10 and Agilex, without this, EMAC PHY wouldn't work correctly. Change-Id: I7e6b9e88fd9ef472884fcf648e6001fcb7549ae6 Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Tien Hock, Loh authored on 2 Oct 2019 Abdul Halim, Muhammad Hadi Asyrafi committed on 24 Feb 2020
2020-02-12	78fcbd6 Browse files » Merge "intel: Change boot source selection" into integration Sandrine Bailleux authored on 12 Feb 2020 TrustedFirmware Code Review committed on 12 Feb 2020
2020-02-05	e1f97d9 Browse files » intel: Extend SiP service to support mailbox's RSU ... Introduce support for RSU that can be initiated through SMC calls. Added features as below: - RSU status - RSU update - RSU HPS notify - RSU get sub-partition Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I78d5a07688e43da99f03d77dfd45ffb4a78f2e4c Hadi Asyrafi authored on 17 Dec 2019 Abdul Halim, Muhammad Hadi Asyrafi committed on 5 Feb 2020
2020-02-03	77fc469 Browse files » intel: Change boot source selection ... Platform handoff structure no longer includes boot source selection. Hence, those settings can now be configured through socfpga_plat_def.h. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: If7ec6a03bb25156a6670ebf8f77105c370b553f6 Hadi Asyrafi authored on 30 Dec 2019 Abdul Halim, Muhammad Hadi Asyrafi committed on 3 Feb 2020
2020-01-28	2a1e086 Browse files » intel: agilex: Enable uboot BL31 loading ... This patch enables uboot's spl entrypoint to BL31 and also handles secondary cpus state during cold boot. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ib70ec91a3ad09a568cb66e7c1e23a2b3e460746c Hadi Asyrafi authored on 13 Jan 2020 Abdul Halim, Muhammad Hadi Asyrafi committed on 28 Jan 2020
2020-01-15	f2decc7 Browse files » intel: Add function to check fpga readiness ... Create a function to check for fpga readiness, and move the checking out of bridge enable function. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I3f473ffeffa9ce181a48977560c8bda19c6123c0 Hadi Asyrafi authored on 24 Dec 2019 Abdul Halim, Muhammad Hadi Asyrafi committed on 15 Jan 2020
	9c8f3af Browse files » intel: Add bridge control for FPGA reconfig ... This is to make sure that bridge access in disabled before doing full FPGA reconfiguration and turn re-enable it once the configuration succeed. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I1f42fbf04ac1625048bbdf21b8a0443464ed833d Hadi Asyrafi authored on 23 Dec 2019 Abdul Halim, Muhammad Hadi Asyrafi committed on 15 Jan 2020
	20335ca Browse files » intel: System Manager refactoring ... Refactored system manager driver to be shared across both intel platform Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ic4d056c3d15c3152403dc11641c2452770a6162d Hadi Asyrafi authored on 23 Dec 2019 Abdul Halim, Muhammad Hadi Asyrafi committed on 15 Jan 2020
	391eeee Browse files » intel: Refactor reset manager driver ... Refactor reset manager into intel common platform directory as it can be shared by both Stratix 10 and Agilex. Register address and field is now referred through macros. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Id6d50f2a2f5a6bd8d6746b84602ac17ec7f6c07a Hadi Asyrafi authored on 23 Dec 2019 Abdul Halim, Muhammad Hadi Asyrafi committed on 15 Jan 2020
	3dcb94d Browse files » intel: Enable bridge access in Intel platform ... Add bridge enablement features for each platform. The bridge access will be enabled automatically for FPGA 1st configuration only. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I264757b257a209e1c3c4206660f21c5d67af0d2f Hadi Asyrafi authored on 21 Oct 2019 Abdul Halim, Muhammad Hadi Asyrafi committed on 15 Jan 2020
	222519a Browse files » intel: Modify non secure access function ... Combine both peripheral and bridge non-secure access code into a single callable function Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I38d335ed8d1e9f55d337b63cca121a473897ef70 Hadi Asyrafi authored on 21 Oct 2019 Abdul Halim, Muhammad Hadi Asyrafi committed on 15 Jan 2020
2020-01-14	bc3579b Browse files » Merge "intel: Fix memory calibration" into integration Manish Pandey authored on 14 Jan 2020 TrustedFirmware Code Review committed on 14 Jan 2020
2020-01-08	7a05f06 Browse files » Remove redundant declarations. ... In further patches, we wish to enable -wredundant-decls check as part of warning flags by default. Change-Id: I43410d6dbf40361a503c16d94ccf0f4cf29615b7 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com> Madhukar Pappireddy committed on 8 Jan 2020
2019-12-29	3d9f726 Browse files » intel: Fix memory calibration ... Increase calibration delay to cater for HPS 1st mode and reduce clear emif delay which takes too long Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I1a50a5d8a6518ba085d853cb636efa07326552b4 Hadi Asyrafi committed on 29 Dec 2019
2019-11-27	1520b5d Browse files » intel: Refactor common platform code [5/5] ... Removes unused source code for BL2 and BL31 in platform.mk. Clean-up unused header files, syntax fixes, and alphabetical sorting post-refactoring Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ie5ea9b4d3abdb0187cddeb04d2fcfb51fbe5c4dd Hadi Asyrafi committed on 27 Nov 2019
	c76d423 Browse files » intel: Refactor common platform code [4/5] ... Pull out SiP & PSCI service driver into socfpga common directory. Remove deassert_peripheral_reset from cold reset procedure as it is not needed. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I1a0390fca6db4c89919a2a038de2a9d96c3ae4fd Hadi Asyrafi committed on 27 Nov 2019
	d09adcb Browse files » intel: Refactor common platform code [3/5] ... Pull out mailbox driver into common area as they can be shared between intel's socfpga platform Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I4064de1ec668931d77abcb7804f6952b70d33716 Hadi Asyrafi committed on 27 Nov 2019
	e9b5e36 Browse files » intel: Refactor common platform code [2/5] ... Share socfpga private definitions and storage driver between Agilex and Stratix 10 platform. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I6da147f4d2df4a97c505d4bbcffadf63bc3bf4a5 Hadi Asyrafi committed on 27 Nov 2019
	328718f Browse files » intel: Refactor common platform code [1/5] ... Pull out handoff driver to intel/soc/ common directory as they can be shared by both Agilex and Stratix10 platform. Share platform_def header between both Agilex and Stratix10 and store platform specific definitions in socfpga_plat_def.h Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I8eff1afd7ee71704a36a54fad732ede4f557878d Hadi Asyrafi committed on 27 Nov 2019
2019-09-12	b90f207 Browse files » Invalidate dcache build option for bl2 entry at EL3 ... Some of the platform (ie. Agilex) make use of CCU IPs which will only be initialized during bl2_el3_early_platform_setup. Any operation to the cache beforehand will crash the platform. Hence, this will provide an option to skip the data cache invalidation upon bl2 entry at EL3 Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I2c924ed0589a72d0034714c31be8fe57237d1f06 Hadi Asyrafi authored on 20 Aug 2019 Soby Mathew committed on 12 Sep 2019
2019-09-12	afac968 Browse files » intel: agilex: Fix psci power domain off ... Disable gic cpu interface for powered down cpu. This patch also removes core reset during power off as core reset will be done during power on Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I2ca96d876b6e71e56d24a9a7e184b6d6226b8673 Hadi Asyrafi committed on 12 Sep 2019
2019-08-28	3441952 Browse files » Merge "intel: agilex: Clear PLL lostlock bypass mode" into integration Paul Beesley authored on 28 Aug 2019 TrustedFirmware Code Review committed on 28 Aug 2019
2019-08-19	24d16a2 Browse files » intel: agilex: HMC driver calculate DDR size ... Driver will calculate DDR size instead of using hardcoded value Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I642cf2180929965ef12bd5ae4393b2f3d0dcddde Hadi Asyrafi committed on 19 Aug 2019
2019-08-18	960a12b Browse files » intel: agilex: Clear PLL lostlock bypass mode ... To provide glitchless clock to downstream logic even if clock toggles Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I728d64d0ba3b4492125bea5b0737fc83180356f1 Hadi Asyrafi committed on 18 Aug 2019
2019-08-15	d1b6013 Browse files » Merge "intel: agilex: Fix memory controller driver" into integration Paul Beesley authored on 15 Aug 2019 TrustedFirmware Code Review committed on 15 Aug 2019