Merge branch 'for-next/arm'

Release v2019.10.0 ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: mmu: use client domain permissions to support ARMv7 eXecute Never ...

The ARM Architecture Reference Manual notes[1]:
> When using the Short-descriptor translation table format, the XN
> attribute is not checked for domains marked as Manager.
> Therefore, the system must not include read-sensitive memory in
> domains marked as Manager, because the XN bit does not prevent
> speculative fetches from a Manager domain.

To avoid speculative access to read-sensitive memory-mapped peripherals
on ARMv7, let's use client domain permissions for all memory, so the XN
bit (and also R/W bits) can function.
This aligns us with what Linux is doing on ARMv7.

This fixes cache corruption instances that had been observed on the
i.MX6UL(L) when the instruction prefetcher speculates into memory following
the end of a 512M SDRAM[2].

While this is not necessary to avoid speculative accesses on < ARMv7,
we could probably have everything there in client domain as well, but
due to lack of test coverage, we'll restrict the change to ARMv7.

[1]: B3.7.2 - Execute-never restrictions on instruction fetching
[2]: "Cache Corruption on MX6UL(L)": https://community.nxp.com/thread/511925

Fixes: 0198567c4 ("ARM: mmu: mark uncached regions as eXecute never on v7")
Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: mmu: set R/W bits in ARMv7 translation table ...

With barebox using the manager permissions for domain 0 that's used for
all page table entries and directories, we never had the need so far to
explicitly set R/W bits. We did so anyway for sections in the early MMU
code, but later on in the normal MMU setup, we didn't do so consistently.

In preparation for switching to DOMAIN_CLIENT for ARMv7, configure R/W
everywhere in normal MMU code as well.

Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: cache-armv7: remove duplicate domain initialization ...

We already call set_domain each time we do __mmu_cache_on. Writing the
DACR in the armv7 __mmu_cache_on is thus superfluous. Drop it.

This changes existing behavior, whereas all 16 memory domains had the same
access permissions set (manager) before, now only the first domain has.
This is ok, as we only ever use domain 0 in barebox and on non-armv7,
we don't bother with the other ones at all.

Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: cache-armv7: remove superfluous instruction ...

There are two tst r11, #0xf with nothing in between them that changes
r11. This a left over from the kernel code that checks for VMSA twice,
once to check if the page table should be setup and once to more to
flush the TLB. We do the setup in the caller already, so the tst serves
no useful purpose. Delete one.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: mmu: remove no longer accurate comment ...

This comment refers to the state of things prior to e3e54c644
("ARM: mmu: Implement on-demand PTE allocation"). Since then, we no
longer generate 2nd level page tables directly below. Remove it
to avoid confusion.

Cc: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: use system.h's get_cr() for cpuinfo ...

Instead of open-coding the get_cr(), use the already available helper
in <asm/system.h> same as we do for 64-bit ARMv8.
The only difference is that the "memory" clobber is replaced by "cc".
This is ok as we don't expect get_cr() to affect memory and because
we do it elsewhere in barebox without a "memory" clobber already.

While at it, move it out the #if/#else clause as the helper changes
behavior depending on the same CONFIG option anyway.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: stm32mp: add bootm handler for images ...

STM32 images are preceded by a fixed-size 256 byte header, which is
interpreted by the TF-A first stage bootloader and isn't executable
as ARM code.

To maintain the ability to network boot them, add a bootm handler that
skips the header.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

fix compile error when set CONFIG_CONSOLE_SIMPLE=y ...

Signed-off-by: DU HUANPENG <u74147@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Documentation: zii-vf610-dev: Fix bogus DDR configuration values ...

There's a clear mismatch between actual TCL code and comment right
next to it. Comments are definetly right, so fix the TCL code.

Fixes: 02738f4b59 ("Documentation: zii-vf610-dev: Reconcile DDR setup with DCD")
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: aarch64: add image markers to linker script ...

The __image_start and __image_end marker are used by barebox to
calculate the size of the barebox binary inside the RAM. Without the
definitions barebox calculates its own size to zero, which works until a
certain size is exceeded, than the PBL will place the binary lower into
memory than the calculation inside barebox.
Fix this by adding the appropriate image markers to the linker script.

Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

input: specialkeys: remove unused printk argument ...

Two pr_info calls have no format specifiers, but are still passed an
argument. Remove the unused arguments.

Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mci: imx-esdhc-pbl: Fix watermark level value for i.MX ...

Layerscape and i.MX have different semantics of Watermark Level
Register. Whereas the former uses "0" to signify maximum allowed
value, the latter does not.

According to the RM (i.MX8MQ, i.MX6):

"...The read burst length must be less than or equal to the read
watermark level.."

Setting Watermark Level Register to zero violates that limitation. It
appears that, on i.MX8MQ, not following that rule causes certain
configs + toolchains to result in non-bootable image. Specifically,
polling for CICHB, CIDHB and DLA to clear in esdhc_send_cmd() times
out. There doesn't appear to be any clear relationship as to what kind
of image will have the problem, but the following combinations failed
to boot on ZII i.MX8MQ Zest board:

  - gcc version 9.2.1 20190827 (Red Hat Cross 9.2.1-1) (GCC) +
    imx_v8_defconfig + CONFIG_DEBUG_LL and CONFIG_PBL_CONSOLE

  - gcc version 5.5.0 (Timesys 20190405) (custom toolchain) +
    imx_v8_defconfig

Setting WML's *_BRST_LE to 16 and *_WML to 128 on i.MX resolves the
issue (same setting that's selected by writing 0 on Layerscape).

Fixes: 48562aeaa8 ("esdhc-xload: check for PRSSTAT_BREN only after each block")
Cc: Chris Healy <cphealy@gmail.com>
Cc: Ruslan Sushko <ruslan.sushko@zii.aero>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Tested-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: aarch64: Re-implement most of barebox_arm_entry() in assembly ...

GCC9 now produces the following warning:

common.h:51:2: warning: listing the stack pointer register ‘sp’ in a clobber list is deprecated [-Wdeprecated]
   51 |  __asm__ __volatile__("mov sp, %0"
      |  ^~~~~~~
common.h:51:2: note: the value of the stack pointer after  an ‘asm’ statement must be the same as it was before the statement

Stack pointer was added to clobber list in commit f9fc8254b2 ("ARM:
Mark SP as being clobbered in arm_setup_stack()") to prevent GCC from
generating code that would corrupt 'boarddata' pointer by trying to
restore it from invalid stack frame.

Interestingly enough, seemingly unrelated change in commit
64d95896cf ("ARM: aarch64: compile with general-regs-only") changed
generated code such that adding SP to clobber list became no longer
necessary.

While the above can probably be a fix by itself, it seems a better and
more future proof approach would be to address the problem at its root
and re-implement offending startup sequence in assembly.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: remove now unused PBL code ...

Single PBL is now built as part of the multi PBL images, so drop the now
unused single PBL code.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Merge single pbl with multi pbl ...

So far we have two different implementations for PBL: One for a single
PBL and one for multiple images. This patch implements the single PBL
case as a special case of the multi PBL case. With this the single PBL
becomes a multi PBL image with the entry point start_pbl.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: drop bultin DTB ...

We can build multiple DTBs into the binary and board code can select
which one to use. Drop the single builtin DTB and let the boards using
it pass the correct one.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Compile dtbs for lowlevel code ...

When no PBL is used then the DTB is used in the real barebox binary. We
already have lwl-y for code which needs to be in PBL when existing and
in the real barebox binary otherwise. Do the same for the DTBs and
compile them with lwl-dtb-y.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mtd: nand: nand_omap_gpmc: Fix mtd_info usage ...

The mtd_info has not been set correctly in the omap gpmc probe.
Remove the mtd_info in the private struct like it has been done in
other nand drivers. And update the driver accordingly.

Fixes: 76b6f74c5397 ("mtd: nand: Embed struct mtd_info into struct nand_chip")

Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: remove PBL_FORCE_PIGGYDATA_COPY ...

This option is unused in the tree, remove it for now. If you need this
option, let me know, we'll find another solution.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

scripts: Remove NETX image tool ...

NETX support has been removed from barebox. Remove its image built tool
as well.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

net: Remove NETX ethernet driver ...

NETX support has been removed from barebox, so remove the ethernet
driver as well.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

serial: Remove NETX serial driver ...

NETX support has been removed from barebox. Remove the serial driver as
well.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: NETX: remove architecture ...

NETX support has been removed from the Kernel, so there's no point in
supporting it in barebox any longer. Remove the architecture.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mtd: nand: Fix retrieving nand_chip from mtd_info ...

With 76b6f74c53 we begin embedding a struct mtd_info into struct
nand_chip. With this mtd_to_nand() must be changed accordingly.

Fixes: 76b6f74c53 ("mtd: nand: Embed struct mtd_info into struct nand_chip")
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: i.MX6qp: Fix location of the enfc_sel mux ...

On the i.MX6qp the enfc_sel mux is at bits 15-17, not on 16-17. Fix
this. During clock tree initialization we reparented the enfc_sel to:

	clk_set_parent(clks[IMX6QDL_CLK_ENFC_SEL], clks[IMX6QDL_CLK_PLL2_PFD2_396M]);

This resulted in a register setting 0b110 for the enfc_sel mux which is
reserved. Apparently this reserved setting resulted in the enfc clock
being driven from pll3_pfd3_454m. This means our enfc clock was the
factor 454/396 too high.

With b534f79112f0 ("clk: imx6: Fix procedure to switch the parent of
LDB_DI_CLK") we happened to disable pll3_pfd3_454m during init, so with
this commit NAND stopped working entirely on i.MX6qp.

Both issues are fixed with this patch

Fixes: b534f79112f0 ("clk: imx6: Fix procedure to switch the parent of LDB_DI_CLK")
Fixes: 92fd61d12723 ("clk: i.MX6: Fix enfc_sel for i.MX6dqp")

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Remove tx53stk5_defconfig ...

The TX53STK5 is covered by the imx_v7_defconfig, so remove the board
specific config file.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Remove tqma53_defconfig ...

The TQMA53 is covered by the imx_v7_defconfig, so remove the board
specific config file.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Remove datamodul-edm-qmx6_defconfig ...

The edm-qmx6 is covered by the imx_v7_defconfig, so remove the board
specific config.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>