ARM: at91: sama5d2: populate $bootsource and $bootsource_instance ...

The BootROM passes us information about the boot medium in r4 and we
already use that in first stage and pass it along to second stage
PBL already. To make use of it, we need to pass it to barebox proper, do
this by writing it in the last 4 bytes of the SRAM. As second stage
always run in DRAM, this is safe to do.

We could also write to SRAM directly from first stage, but at91bootstrap
passes info in r4 as well for the sama5d3 boards, so we do it likewise
to maintain compatibility.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: sama5d2: read back memory size from DDRAM controller ...

We hard code memory size at three places:
 - In the configuration we use to initialize the DDRAM controller
 - In the minimal available size passed from PBL to barebox proper
 - In the device tree memory node override

Remove the two latter ones and replace them with code that reads the
size back from controller.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: sama5d27-som1: add additional first stage entry point ...

The BootROM constrains us to a 64K big first stage bootloader. Add a PBL
entry point for a xload barebox that sets up the minimum necessary to
load a FAT32 barebox.bin from the SD-Card.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: sama5d2: reduce UART setup boilerplate with new helpers ...

The sama5d2 can be fused for one of 9 preset UART iosets. This is then
used by the BootROM for printing the `RomBOOT' header and for the XMODEM
protocol implemented by the SAM-BA monitor. Add two new sama5d2 specific
helpers:

- sama5d2_dbgu_setup_ll for setting up the port with only pinmux and
  master clock as arguments
- sama5d2_resetup_uart_console for resetup of the uart console with
  same pinmux used by the ROM code

The default value, when unfused, is UART_1_IOSET_1 (RX@PD2, TX@PD3),
which are the same ones used on the two sama5d2 board supported so far.

With this change, the DEBUG_LL baudrate is also no longer fixed at 115200,
but instead comes from the CONFIG_BAUDRATE symbol.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: debug_ll: remove duplicated IS_ENABLED(CONFIG_DEBUG_LL) condition ...

There are three users of at91_dbgu_setup_ll and all already call this
function only when IS_ENABLED(CONFIG_DEBUG_LL). Remove the duplicated
condition from the function itself. This allows us to use the function
for pbl_set_console use later on, even with DEBUG_LL disabled.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: sama5d2: reuse stack set-up by first stage ...

Stack is always set up to end of SRAM before PBL, either by ROM code or
by first stage bootloader, be it at91bootstrap or barebox in a later
commit, so no need to change the stack pointer again.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: add helpers for chain-loading barebox from SD-card ...

With PBL FAT support implemented, provide an sama5d2_sdhci_start_image
helper that can be called from the PBL to chainload a barebox.bin file
from the first FAT partition.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: add code for sama5 boot source detection ...

SAMA5 BootROM passes information about the boot source in the r4
register. Add functions to parse these. To make use of this, entry point
must back up the r4 register, because otherwise it's clobbered by local
variable use.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mci: sdhci: atmel: extend driver for PBL usage ...

The BootROM resets both the SD/MMC host controller and the pin controller,
but the card itself remains in transfer mode. If we redo host-side
setup, we can directly read new blocks off the card.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

fs: fat: extend for in-PBL support ...

The AT91 BootROM loads a boot.bin file from the first FAT partition
into SRAM, when booting from MMC. To avoid the need for two barebox
configurations for each of the bootloader stages, add PBL support
for reading from FAT. This way each stage need only have a different
PBL entry point.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

pbl: add block I/O API ...

We already have some PBL MCI implementations in barebox, but none
are used for chainloading a barebox from a file system.

There are some SoCs that would benefit from this however:
At least the Zynq, AT91, SoCFPGA and TI SoCs.

In preparation for supporting first stage boot on these where it's
customary for both the BootROM and first stage bootloader to load the
follow-up stage from FAT, add a very basic block I/O API that MCI
drivers can implement.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: extend low level PMC driver for generic clk support ...

The SAMA5D2 and SAM9X60 both feature generic clocks, which we already
support in barebox proper, but not in PBL. Add PBL support for setting
the parent and enabling them, so we may use it to enable the SDMMC
peripherals in first stage.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: add necessary Advanced Interrupt Controller configuration ...

Without reconfiguration of the AIC redirection, the OS interrupt
handling will misbehave later on. Add it to the SoC init.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: add sama5d2 cache init ...

The L2 cache controller needs some initialization before use. Same goes
for the CAN SRAM, do so after the MMU setup.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: sama5d2: add sama5d2 matrix configuration ...

Different peripherals, including the SDRAM, are unusable without prior
matrix configuration. Port over the necessary at91bootstrap parts for
sama5d2 use.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: implement sama5d2 lowlevel init ...

Port over the low level initialization for sama5d2 SoCs from
at91bootstrap.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

watchdog: add support for at91sam9/sama5 watchdog ...

The watchdog on these SoCs is enabled by default on system boot, so a
driver is especially useful. According to data sheet the mode register
containing the timeout can be configured only once, but I couldn't
verify this on the sama5d2. Regardless, the driver takes care not to
change the mode register unless necessary. Implementation that want to
leave to the OS the decision which timeout to choose, can just keep
pinging with the POR-default of 16 seconds and the OS will be able to
set the final timeout.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: watchdog: implement at91_wdt_disable ...

Board code might want to disable the watchdog in PBL and enable it later
prior to boot. Provide a helper to do so.

Reviewed-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: import low level DDRAMC initialization code from at91bootstrap ...

This commit imports DDRAMC initialization routines for use in PBL from
https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/driver/ddramc.c

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: import early_udelay from at91bootstrap ...

For use by the incoming at91bootstrap DDRAMC initialization code,
this commit provides an early_udelay function usable in PBL imported from
https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/driver/at91_pit.c

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: replace at91sam9_ddrsdr.h with at91bootstrap's at91_ddrsdrc.h ...

Instead of adding missing definitions to the existing at91sam9_ddrsdr.h
and adapting the incoming DDRAM initialization code from at91bootstrap,
just replace the lightly used existing header with:
https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/include/arch/at91_ddrsdrc.h

For easier comprehension, the replacement is done in three steps:
This last step copies the memory size querying functions from at91sam9_ddrsdr.h
to at91_ddrsdrc.h, then deletes it and fixes all references.

Reviewed-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: migrate at91sam9_ddrsdr.h to use at91bootstrap's at91_ddrsdrc.h ...

Instead of adding missing definitions to the existing at91sam9_ddrsdr.h
and adapting the incoming DDRAM initialization code from at91bootstrap,
just replace the lightly used existing header with:
https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/include/arch/at91_ddrsdrc.h

For easier comprehension, the replacement is done in three steps:
Here the existing at91sam9_ddrsdr.h has its now duplicate (in function,
not name) macros removed and existing users are migrated to use the new
header.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: import at91bootstrap's at91_ddrsdrc.h ...

Instead of adding missing definitions to the existing at91sam9_ddrsdr.h
and adapting the incoming DDRAM initialization code from at91bootstrap,
just replace the lightly used existing header with:
https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/include/arch/at91_ddrsdrc.h

For easier comprehension, the replacement is done in three steps:
Here the header is imported.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: sama5d2: cast peripheral base addresses to __iomem pointers ...

The peripheral addresses should be always cast with IOMEM() anyway, so do
this directly in the header to make user code less verbose.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: remove <mach/hardware.h> include from assembly code ...

They are unused and force all headers included by it to have
__ASSEMBLY__ guards for non-preprocessor code. Avoid this.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mci: sdhci: atmel: avoid buggy SDHCI_RESET_ALL ...

On the sama5d27, currently only the MCI used for boot is operational.
The other one errors out when failing to reset the card.

Changing the RESET_ALL to RESET_CMD | RESET_DATA fixes this.
This might be due to the SoC's "11.1   Software 'Reset For all'
command may not execute properly" erratum[1]:
> The software 'Reset For All' command may not execute properly, and, as
> a result, some registers of the host controller may not reset properly.
> The setting of the different registers must be checked beforere
> initializing the SD card.

[1]: DS80000827A

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mci: sdhci: atmel: use dev_printf instead of pr_print in common code ...

On boards like the sama5d27 som1 ek, we have two SD card slots, so error
messages are more useful if they refer to the SDHCI instance. We didn't
do this at first, because the common code is compiled for PBL as well.
With a sprinkle of preprocessor ifdeffery, we can have both.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mci: sdhci: atmel: don't print errors on command timeouts ...

Time outs can be expected, e.g. when probing whether a card is a MMC
one. The core handles it, so don't have the driver print an error.

While at it, simplify the error handling. We don't need to read the
status more than once and returning -EPERM on non-timeout is what the
other drivers are doing.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: choose proper parent for both MCI clocks ...

When booting from SDMMC0, Use of SDMMC1 fails with:
ERROR: clk: couldn't set sdmmc1_gclk clk rate to 480000000 (-22), current rate: 32768

This is because the first stage bootloader only reparents the boot SDMMC
instance and barebox does no automatic reparenting for the other one.

Force both clocks to have a suitable parent.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

clk: sync of_clk_get_parent_name with upstream ...

Upstream of_clk_get_parent_name only resorts to node name as a fallback.
Instead, it uses the name supplied for registered clocks whenever
possible. On the sama5d2, this results in sckc@f8048050 and slowck,
respectively. So far, sckc@f8048050 in the parents array couldn't be
matched with any existing clock, leading to an inaccurate clock tree.

Port over the v5.8-rc1 state of the function to fix this.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>