LICENSES: add LGPL-2.1-or-later ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

include: add SPDX GPL-2.0-only license tags for files without licensing information ...

According to our /README, GPL-2.0-only applies for the whole project
except noted otherwise.

Signed-off-by: Roland Hieber <rohieb@rohieb.name>
Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

include: add SPDX GPL-2.0-or-later license tags where applicable ...

Signed-off-by: Roland Hieber <rohieb@rohieb.name>
Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

include: add SPDX GPL-2.0-only license tags where applicable ...

Interpret "GPLv2" as "GPLv2 only".

Signed-off-by: Roland Hieber <rohieb@rohieb.name>
Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

serial: ns16550_pci: fix possible read of uninitialized variable ...

When quirk->init is NULL, we evaluate an uninitialized rc.
Is we have already checked for rc < 0 at the point of assignment,
this if clause isn't needed. Remove it.

Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

hw_random: add support for STM32 RNG ...

Port over the U-Boot v2020.01.0 state of the driver.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

doc: bootchooser: Fix barebox-state example ...

- Fix prefix
- attemps --> attempts
- add missing equal sign
- Add 2 examples

Signed-off-by: Christian Eggers <ceggers@arri.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

acpi: include missing header in <acpi.h> ...

acpi_sigcmp defined in the header uses memcmp, but no included headers
pull in memcmp, which can lead to compile errors in new code, depending
on include order. Fix this.

Reported-by: @healytpk, https://github.com/saschahauer/barebox/issues/7
Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

RISC-V: unbreak built-in dtb ...

The commit c5d38e92010174 ("lds: Add and use RO_DATA_SECTION macro")
consolidates all RO sections link script declaration in the single
RO_DATA_SECTION macro. So all all individual RO section declarations
have to be removed from per-arch linker scripts.

Alas the BAREBOX_CLK_TABLE and the BAREBOX_DTB link script sections
were not removed from RISC-V linker script making these sections
declared twice. As a result incorrect __clk_of_table_start and
__dtb_start addresses are passed to the barebox code therefore
the RISC-V barebox is completely unusable.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

MIPS: don't overlay relocation data with BSS ...

.bss __rel_start (OVERLAY) was used to optimize RAM size used by
barebox. Since .bss and __rel_start overlap, we should clear bss only
after __rel_start was used. Following patch changed initialization
sequence to clear .bss before __rel_start:
1e5aef61fc6a444 ("MIPS: reloc: init bss and cpu")

This make relocation buffer unusable and broke relocation with different
symptoms reported by Antony Pavlov <antonynpavlov@gmail.com>:
  * iomem output has no information on sdram regions, so memtest is unusable;
  * pc = 0xa081232c, relocation does not work, barebox is located with 8M offset
    from start of RAM. The board has 256M and relocation routine
    should move barebox code much higher;
  * pc = 0xa081232c, so barebox code works from KSEG1 not from KSEG0 as MMU=y option implies.

There is a choice of moving .bss clear sequence after __rel_start or
remove this optimization. Since the use of this optimization is minimal
and danger to trap in to similar issue is still high, i prefer to remove
this optimization.

As result of this change, we need to fix calculation of relocation are
size:
relocate_code() calculates relocation area size as a sum (barebox_image_size +
bss_len). barebox_image_size and bss_len are calculated as (__image_end -
__image_start) and (__bss_stop - __bss_start) respectively. This doesn't take
into account relocation data placed between  __image_end and __bss_start.
However relocation preserves BSS position relative to image start, as if
relocation data is still there. This causes RAM overflow during BSS
initialization in main_entry(). This problem may be hidden due to the alignment
of the `relocaddr`.

Reported-by: Antony Pavlov <antonynpavlov@gmail.com>
Fixes: 1e5aef61fc6a444 ("MIPS: reloc: init bss and cpu")
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Peter Mamonov <pmamonov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mci: stm32_sdmmc2: fix typo in debug string ...

s/bus_with/bus_width/

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mci: stm32_sdmmc2: compare ios ->bus_width with correct constants ...

MMC_BUS_WIDTH_4 != 4 && MMC_BUS_WIDTH_8 != 8.

This enables driver support for 4-bit SD-Cards and 8-bit MMCs,
which before was disabled because of CRC errors:

  ERROR: error SDMMC_STA_DCRCFAIL (0x81042) for cmd 18
  ERROR: stm32_sdmmc2_end_cmd: error SDMMC_STA_CTIMEOUT (0x4) for cmd 12

These happened because the card was correctly instructed to use the new
bus width, but the controller wasn't.

Cc: Oleksij Rempel <o.rempel@pengutronix.de>
Fixes: ce99d0c86b32ec ("mci: add support for stm32mp sd/mmc controller")
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mci: core: don't test 4-bit-buswidth support if MMC host lacks capability ...

We already check for MMC_CAP_8_BIT_DATA before trying if buswidth=8
yields legible data. For consistency, don't test whether buswidth=4
works if the MMC host doesn't indicated MMC_CAP_4_BIT_DATA.

Fixes: 68db956d ("mci: Fix 8 bit mmc cards")
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mci: stm32_sdmmc2: don't reset before retrying failed operations ...

The original U-Boot code doesn't do this and it wipes the configured
settings like clock rate, ensuring that we won't ever recover from the
error. Drop it.

Fixes: ce99d0c86b32ec ("mci: add support for stm32mp sd/mmc controller")
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mci: stm32_sdmmc2: use correct card power cycle sequence ...

The stm32mp157c RM0436 reference manual lists following sequence for
resetting the SDMMC:

1. Reset using the RCC.SDMMCxRST register bit
  -> We do this via reset_control_assert

2. Disable Vcc power to the card
  -> We don't do this, because the rail often has other 3v3 peripherals
     hanging off it

3. Set the SDMMC to power-cycle state
  -> We do this only when the MCI core sets the frequency to zero, not
     on init!

4. reenable Vcc power to the card after a >1ms
  -> We don't do this, because we don't disable Vcc

5. Wait >1ms for the power ramp period, then put card into power-off
  -> We do this in stm32_sdmmc2_pwron

6. Wait >1ms, then put card into power-on state
  -> We do this in stm32_sdmmc2_pwron

7. Wait 74 SDMMC_CK cycles before sending the first command to the card
  -> We don't have an explicit delay between mci_startup_{sd,mmc} and
     mci_set_blocklen, so a low max-speed may run afoul of the timing
     constraint

Fix 3 & 7. 3 is the main one and doing it fixes an issue of timeouts
occurring, when having barebox in a reboot loop or the SD-Card inside
a USB-SD-Mux.

Fixes: ce99d0c86b32ec ("mci: add support for stm32mp sd/mmc controller")
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: imx6: properly check for IPU presence ...

Since a73850bd76d0 (ARM: imx: disable IPU QoS setup for correct SoCs), which
fixed the condition to not execute the IPU QoS fixups on SoCs that don't have
a IPU, the fixups aren't applied on i.MX6Q/DP anymore, since those SoCs were
missing from the whitelist.

Add a function to make it a bit more clearer what we are checking here and add
the Q/DP SoCs.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

net: designware: eqos: don't funnel all MDIO writes to register 0 ...

eqos_mdio_write ended up using the addr parameter instead of the
computed miiaddr variable, which would've factored in the reg parameter.

This had the effect that all writes went to PHY register 0, which was
fine as long as there were only register 0 writes. As soon there are more
writes, e.g. because a PHY driver was enabled, register 0 became
clobbered and erratic behavior ensued.
Fix the typo and while at it rename the val parameter to a more
descriptive name.

Fixes: a4f709bbb ("net: add Designware Ethernet QoS for STM32MP")
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

MIPS: actually use CONFIG_MIPS_RELOCATION_TABLE_SIZE ...

The commit 28ed10d6a67c9 ("MIPS: relocation: add relocation support")
introduce the Kconfig CONFIG_MIPS_RELOCATION_TABLE_SIZE parameter
but it is never used.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Revert "clocksource: ARMv8 timer can only be built on ARMv8" ...

This reverts commit 33ec8cb,
so that barebox can once again match against "arm,armv7-timer"
compatibles. The reverted commit restricted the timer to CPU_V8,
because in i.MX multi-image configuration with MACH_SCB9328 set,
we can have both CPU_32v7 and CPU_32v4T in the same build.

To avoid this issue properly, force use of -march=armv7-a for
non-CONFIG_CPU_V8 targets. This is acceptable as we don't expect
non-ARMv7 device trees to have the architected arm,armv7-timer.

Suggested-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: qemu-virt64: convert to assembly entry ...

The C entry function isn't naked, so tries to push to the stack
in the function prologue. This doesn't work on QEMU where there
is no valid SP on entry. Convert the lowlevel entry to the
assembly facilities provided for this case.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/zynq'

Merge branch 'for-next/rpi'

Merge branch 'for-next/misc'

Merge branch 'for-next/led'

Merge branch 'for-next/layerscape'

Merge branch 'for-next/imx'

Merge branch 'for-next/dts'

Merge branch 'for-next/arm'

dts: update to v5.5-rc6 ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

dts: update to v5.5-rc5 ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>