eeprom: at25: Allow page sizes greater than 16 bit ...

For FRAM devices the page size is usually equal to the device size. Some
available devices are greater than 64kB, so a 32 bit variable must be
used.

The same change has to be done for the Linux driver. I'll try to
upstream this as soon as possible.

Signed-off-by: Christian Eggers <ceggers@arri.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

watchdog: Fix error path ...

In case of an error (e.g. dev_add_param_tristate_ro() returns -ENOSYS),
device registration must be reverted.

Signed-off-by: Christian Eggers <ceggers@arri.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

param: Make enum param_tristate always visible ...

When disabling CONFIG_SHELL_HUSH, also CONFIG_PARAMETER may be disabled.
In this case, the definition "enum param_tristate" is not reachable from
watchdog.h.

I also considered moving almost everything in watchdog.h inside the
CONFIG_WATCHDOG guard. But this doesn't work for me because
drivers/watchdog/imxwd.c can also be built without CONFIG_WATCHDOG.

Signed-off-by: Christian Eggers <ceggers@arri.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

pinctrl-single: Handle "pinctrl-single,function-mask" dt property ...

Implement linux behavior regarding "pinctrl-single,function-mask" and
"pinctrl-single,bits".
It allows multiple pins control per register.

(linux sha1: 4e7e801)

Signed-off-by: Simeon Marijon <simeon@marijon.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

net: designware: eqos: don't funnel all MDIO writes to register 0 ...

eqos_mdio_write ended up using the addr parameter instead of the
computed miiaddr variable, which would've factored in the reg parameter.

This had the effect that all writes went to PHY register 0, which was
fine as long as there were only register 0 writes. As soon there are more
writes, e.g. because a PHY driver was enabled, register 0 became
clobbered and erratic behavior ensued.
Fix the typo and while at it rename the val parameter to a more
descriptive name.

Fixes: a4f709bbb ("net: add Designware Ethernet QoS for STM32MP")
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

MIPS: actually use CONFIG_MIPS_RELOCATION_TABLE_SIZE ...

The commit 28ed10d6a67c9 ("MIPS: relocation: add relocation support")
introduce the Kconfig CONFIG_MIPS_RELOCATION_TABLE_SIZE parameter
but it is never used.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Revert "clocksource: ARMv8 timer can only be built on ARMv8" ...

This reverts commit 33ec8cb,
so that barebox can once again match against "arm,armv7-timer"
compatibles. The reverted commit restricted the timer to CPU_V8,
because in i.MX multi-image configuration with MACH_SCB9328 set,
we can have both CPU_32v7 and CPU_32v4T in the same build.

To avoid this issue properly, force use of -march=armv7-a for
non-CONFIG_CPU_V8 targets. This is acceptable as we don't expect
non-ARMv7 device trees to have the architected arm,armv7-timer.

Suggested-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: qemu-virt64: convert to assembly entry ...

The C entry function isn't naked, so tries to push to the stack
in the function prologue. This doesn't work on QEMU where there
is no valid SP on entry. Convert the lowlevel entry to the
assembly facilities provided for this case.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/zynq'

Merge branch 'for-next/rpi'

Merge branch 'for-next/misc'

Merge branch 'for-next/led'

Merge branch 'for-next/layerscape'

Merge branch 'for-next/imx'

Merge branch 'for-next/dts'

Merge branch 'for-next/arm'

dts: update to v5.5-rc6 ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

dts: update to v5.5-rc5 ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Release v2020.01.0 ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

MIPS: dts: rename tplink-mr3020.dts -> ar9331_tl_mr3020.dts ...

Linux MIPS uses <soc-name>_<board-name>.dts board dts-file
naming scheme so use it in barebox too.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

usb: ehci: Do not use memset on dma coherent memory ...

memset is an optimized operation that at least on ARM64 may only be
called on cached memory, see 32e8842c40 ("ARM: lib64: Make string
functions aware of MMU configuration"). To avoid crashes in the ehci
driver we no longer call memset on memory allocated with
dma_alloc_coherent(), but use a simple memzero32 function instead.

Reported-by: Elmar Albert <EAlbert@data-modul.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: zynq: zedboard: add PBL console support ...

Allows for significantly easier debugging of PBL functions.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

serial: cadence: add lowlevel init and putc functions ...

This allows to use the Cadence serial as a PBL console.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

serial: cadence: move register definitions into header file ...

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: zynq: zed: partially revert zynq_cpu_lowlevel_init() chnages ...

Calling arm_cpu_lowlevel_init() from zynq_cpu_lowlevel_init() adds a stack
push/pop to the latter function which doesn't work this early in the boot.

As the BootROM apparently hands proccessor control to us in abort(!?!)
mode, setting up a stack requires duplicating most of arm_cpu_lowlevel_init().
To get around this catch-22 move the call to arm_cpu_lowlevel_init back into
the board lowlevel start function, so we don't need a stack at all.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: layerscape: Fixup iommu-map properties ...

The iommu-map properties are needed for proper PCI support under Linux.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: layerscape: rename variable ...

Rename 'arr' to 'msi_map' which is a better name when we add another
array in the next patch.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Layerscape: setup icids for the IOMMU ...

The Isolation Context Identifiers (icid) have to be configured in the
hardware and communicated to the Kernel via device tree fixups. This
adds the missing bits and pieces to make the IOMMU work under Linux.

As of Linux-5.5 the SMMU doesn't work out of the box. This series has
been tested in conjunction with this Kernel series:
https://lore.kernel.org/patchwork/cover/997994/

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

net: fsl-fman: Do not put hardware in reset before Linux start ...

Linux depends on the icid values configured in the DPAA. Do not put
the hardware into reset in order to preserve the register values.
Without this, the IOMMU doesn't work properly.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

include/soc/fsl: Make struct ccsr_qman v3 specific ...

struct ccsr_qman is ifdeffed for different versions of this structure.
CONFIG_SYS_FSL_QMAN_V3 is not defined which means we happen to use
the wrong version on LS1046a. Hardcode it to the v3 version to make
it work on LS1046a and rename it to ccsr_qman_v3 to make it obvious
that it needs a change on non v3 versions.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>