mci: stm32_sdmmc2: fix typo in debug string ...

s/bus_with/bus_width/

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mci: stm32_sdmmc2: compare ios ->bus_width with correct constants ...

MMC_BUS_WIDTH_4 != 4 && MMC_BUS_WIDTH_8 != 8.

This enables driver support for 4-bit SD-Cards and 8-bit MMCs,
which before was disabled because of CRC errors:

  ERROR: error SDMMC_STA_DCRCFAIL (0x81042) for cmd 18
  ERROR: stm32_sdmmc2_end_cmd: error SDMMC_STA_CTIMEOUT (0x4) for cmd 12

These happened because the card was correctly instructed to use the new
bus width, but the controller wasn't.

Cc: Oleksij Rempel <o.rempel@pengutronix.de>
Fixes: ce99d0c86b32ec ("mci: add support for stm32mp sd/mmc controller")
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mci: core: don't test 4-bit-buswidth support if MMC host lacks capability ...

We already check for MMC_CAP_8_BIT_DATA before trying if buswidth=8
yields legible data. For consistency, don't test whether buswidth=4
works if the MMC host doesn't indicated MMC_CAP_4_BIT_DATA.

Fixes: 68db956d ("mci: Fix 8 bit mmc cards")
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mci: stm32_sdmmc2: don't reset before retrying failed operations ...

The original U-Boot code doesn't do this and it wipes the configured
settings like clock rate, ensuring that we won't ever recover from the
error. Drop it.

Fixes: ce99d0c86b32ec ("mci: add support for stm32mp sd/mmc controller")
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mci: stm32_sdmmc2: use correct card power cycle sequence ...

The stm32mp157c RM0436 reference manual lists following sequence for
resetting the SDMMC:

1. Reset using the RCC.SDMMCxRST register bit
  -> We do this via reset_control_assert

2. Disable Vcc power to the card
  -> We don't do this, because the rail often has other 3v3 peripherals
     hanging off it

3. Set the SDMMC to power-cycle state
  -> We do this only when the MCI core sets the frequency to zero, not
     on init!

4. reenable Vcc power to the card after a >1ms
  -> We don't do this, because we don't disable Vcc

5. Wait >1ms for the power ramp period, then put card into power-off
  -> We do this in stm32_sdmmc2_pwron

6. Wait >1ms, then put card into power-on state
  -> We do this in stm32_sdmmc2_pwron

7. Wait 74 SDMMC_CK cycles before sending the first command to the card
  -> We don't have an explicit delay between mci_startup_{sd,mmc} and
     mci_set_blocklen, so a low max-speed may run afoul of the timing
     constraint

Fix 3 & 7. 3 is the main one and doing it fixes an issue of timeouts
occurring, when having barebox in a reboot loop or the SD-Card inside
a USB-SD-Mux.

Fixes: ce99d0c86b32ec ("mci: add support for stm32mp sd/mmc controller")
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: imx6: properly check for IPU presence ...

Since a73850bd76d0 (ARM: imx: disable IPU QoS setup for correct SoCs), which
fixed the condition to not execute the IPU QoS fixups on SoCs that don't have
a IPU, the fixups aren't applied on i.MX6Q/DP anymore, since those SoCs were
missing from the whitelist.

Add a function to make it a bit more clearer what we are checking here and add
the Q/DP SoCs.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

net: designware: eqos: don't funnel all MDIO writes to register 0 ...

eqos_mdio_write ended up using the addr parameter instead of the
computed miiaddr variable, which would've factored in the reg parameter.

This had the effect that all writes went to PHY register 0, which was
fine as long as there were only register 0 writes. As soon there are more
writes, e.g. because a PHY driver was enabled, register 0 became
clobbered and erratic behavior ensued.
Fix the typo and while at it rename the val parameter to a more
descriptive name.

Fixes: a4f709bbb ("net: add Designware Ethernet QoS for STM32MP")
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

MIPS: actually use CONFIG_MIPS_RELOCATION_TABLE_SIZE ...

The commit 28ed10d6a67c9 ("MIPS: relocation: add relocation support")
introduce the Kconfig CONFIG_MIPS_RELOCATION_TABLE_SIZE parameter
but it is never used.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Revert "clocksource: ARMv8 timer can only be built on ARMv8" ...

This reverts commit 33ec8cb,
so that barebox can once again match against "arm,armv7-timer"
compatibles. The reverted commit restricted the timer to CPU_V8,
because in i.MX multi-image configuration with MACH_SCB9328 set,
we can have both CPU_32v7 and CPU_32v4T in the same build.

To avoid this issue properly, force use of -march=armv7-a for
non-CONFIG_CPU_V8 targets. This is acceptable as we don't expect
non-ARMv7 device trees to have the architected arm,armv7-timer.

Suggested-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: qemu-virt64: convert to assembly entry ...

The C entry function isn't naked, so tries to push to the stack
in the function prologue. This doesn't work on QEMU where there
is no valid SP on entry. Convert the lowlevel entry to the
assembly facilities provided for this case.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/zynq'

Merge branch 'for-next/rpi'

Merge branch 'for-next/misc'

Merge branch 'for-next/led'

Merge branch 'for-next/layerscape'

Merge branch 'for-next/imx'

Merge branch 'for-next/dts'

Merge branch 'for-next/arm'

dts: update to v5.5-rc6 ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

dts: update to v5.5-rc5 ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Release v2020.01.0 ...

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

MIPS: dts: rename tplink-mr3020.dts -> ar9331_tl_mr3020.dts ...

Linux MIPS uses <soc-name>_<board-name>.dts board dts-file
naming scheme so use it in barebox too.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

usb: ehci: Do not use memset on dma coherent memory ...

memset is an optimized operation that at least on ARM64 may only be
called on cached memory, see 32e8842c40 ("ARM: lib64: Make string
functions aware of MMU configuration"). To avoid crashes in the ehci
driver we no longer call memset on memory allocated with
dma_alloc_coherent(), but use a simple memzero32 function instead.

Reported-by: Elmar Albert <EAlbert@data-modul.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: zynq: zedboard: add PBL console support ...

Allows for significantly easier debugging of PBL functions.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

serial: cadence: add lowlevel init and putc functions ...

This allows to use the Cadence serial as a PBL console.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

serial: cadence: move register definitions into header file ...

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: zynq: zed: partially revert zynq_cpu_lowlevel_init() chnages ...

Calling arm_cpu_lowlevel_init() from zynq_cpu_lowlevel_init() adds a stack
push/pop to the latter function which doesn't work this early in the boot.

As the BootROM apparently hands proccessor control to us in abort(!?!)
mode, setting up a stack requires duplicating most of arm_cpu_lowlevel_init().
To get around this catch-22 move the call to arm_cpu_lowlevel_init back into
the board lowlevel start function, so we don't need a stack at all.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: layerscape: Fixup iommu-map properties ...

The iommu-map properties are needed for proper PCI support under Linux.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: layerscape: rename variable ...

Rename 'arr' to 'msi_map' which is a better name when we add another
array in the next patch.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: Layerscape: setup icids for the IOMMU ...

The Isolation Context Identifiers (icid) have to be configured in the
hardware and communicated to the Kernel via device tree fixups. This
adds the missing bits and pieces to make the IOMMU work under Linux.

As of Linux-5.5 the SMMU doesn't work out of the box. This series has
been tested in conjunction with this Kernel series:
https://lore.kernel.org/patchwork/cover/997994/

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>