usb: gadget: allow to actually enable sparse fastboot support ...

When sparse support was (intended to be) made optional it was
effectively unconditionally disabled because

	IS_ENABLED(USB_GADGET_FASTBOOT_SPARSE)

always evaluates to 0. To actually make use of the introduced kconfig
symbol the CONFIG_ prefix must not be skipped.

Fixes: f4b5d3eeb607 ("usb: gadget: fastboot: Make sparse support optional")
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Tested-by: Gavin Schenk <g.schenk@eckelmann.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mci: s3c: fix providing info callback ...

There is no symbol iCONFIG_MCI_INFO, CONFIG_MCI_INFO makes sense here
and matches what was added in the same commit to other drivers.

Fixes: 73b0d228e5b0 ("driver: Attach info callback to device, not to driver")
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

of_node: clarify help text and do stricter commandline parsing ...

To create an oftree node /path/node I tried after reading the help text
of of_node:

	of_node -c /path node

similar to the syntax of of_property. This didnt result in any output
but still failed to do what I meant.

So clarify the help text to not suggest there are two parameters and
return an usage error if still two (or more) names are passed.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: imx6: gw54xx: add fixup for PCIe switch ...

After the PCIe switch has been scanned its GPIOs need to be
configured as output-high to release the devices behind the
switch from their reset state and make them discoverable to
the bus scan.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

pci: add quirk infrastructure ...

This is a cut down version of the Linux kernel PCI quirk infrastructure,
which allows to register and execute some fixups before the driver is
loaded.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

PCI: link PCI devices with potentially existing OF nodes ...

The document "PCI Bus Binding to: IEEE Std 1275-1994 Standard for Boot
(Initialization Configuration) Firmware" describes how the PCI topology
can be described in the DT, in order to augment the PCI devices with
additional information via DT properties.

This patch links OF nodes to the corresponding PCI devices if they
exist, allowing PCI device drivers to query DT information like any
platform device.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: socfpga: achilles: move environment to raw partition ...

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: arria10: update defconfig ...

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: socfpga: achilles: convert to PBL barebox ...

Previously the FPGA was configured externally on the Achilles. On newer versions
this is changed and barebox has to configure the FPGA before the SDRAM can be
used.

If the FPGA is configured via JTAG or from an external memory, the *-bringup
version can be used.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: socfpga: Arria10: support programming FPGA in PBL ...

Some Arria10 boards don't have the FPGA programmed externally.
Instead barebox needs to do that. As the Arria10 has the SDRAM
controller in the FPGA, the first thing we need to do is,
configure the FPGA before the SDRAM can even be used.

It works like this:
  1. boot ROM fetches the PBL from MMC
  2. read the MBR from MMC (this depends on the setup done by the boot ROM)
  3. read the Bitstream from the MMC and program the FPGA
  4. re-read the barebox image from MMC, this time with the full barebox
     that is appended to the PBL
  5. jump into the full barebox

Only supported boot device is eMMC.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: socfpga: arria10-reset-manager: don't reset bootsource ...

Arria10 init code resets all peripherals. Convert this to keep the bootmedium
out of reset and keep the setup done by the boot ROM.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

scripts: socfpga_mkimage: add size feature for PBL barebox ...

Add the switch 's' to fixup the image size into the barebox header.
This is used by the Arria10 PBL code to know the complete image size.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: dts: socfpga: Fix achilles dtc warnings ...

The newer dtc has stricter checks on devicetrees. Fix the warnings.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: socfpga: achilles: update handoff files ...

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: socfpga: arria10: fix SDMMC phase shift ...

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: socfpga: arria10: set default TEXTBASE ...

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: socfpga: arria10-init: split pinsetup ...

Move the setup of the shared- and fpgapins to its own function.
These pins can only be configured and let out of reset after the FPGA has been
programmed.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: socfpga: add SMP_TWD_ADDR for Arria10 ...

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: socfpga: arria10: add ocram base address ...

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: socfpga: arria10: move debug_ll to common code ...

Instead of copy+pasting the debug_ll messages to every new board,
move them to the respective functions.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

bootm: allow booting SoCFPGA prebootloader image ...

A prebootloader image might also contain a fully working barebox and
allows to be booted second stage. Thus we add a handler here to give it
a try.

Signed-off-by: Enrico Jorns <ejo@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mci: dw: move defines to headerfile ...

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mci: dw_mmc: convert to BIT() macro ...

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

mci: dw_mmc: remove device_d pointer ...

The pointer to the struct device_d *dev is also saved to the struct mci_host.
Get rid of it.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

reset: socfpga: add missing driver name ...

The driver_d is missing the name property. When the reset driver is used in a
non-of setup, this will result in an error during device_registration where
the dev->name is matched to the driver->name.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX: fix compilation with BBU disabled ...

Make a static inline wrapper actually static inline.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Documentation: don't highlight literal blocks as shell script ...

There are multiple cases in the documentation where literal blocks are
used for literal, preformatted text. Although it is possible to use
`.. code-block: none` in these cases instead of literal `::` blocks,
follow the principle of least surprise and don't apply any syntax
highlighting at all for literal blocks.

Signed-off-by: Roland Hieber <r.hieber@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX: fimware: Add pre-built BL31 ATF blob ...

Running Linux on i.MX8M requires us to use and properly set up a ARM
Trusted Firmware blob. For the sake of convenience, add a pre-built
blob to our firmware tree, so it can be used by individual boards.

This blob was built using Buildroot:

 - commit: 6b02b82
 - defconig: freescale_imx8mqevk_defconfig

The resulting file of interest is output/images/bl31.bin

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX8MQ: Add code to load BL31 ATF blob ...

Add imx8mq_atf_load_bl31() containing all of the code needed to load
and transfer control to BL31 ATF blob on i.MX8M.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX8MQ: Configure cntfrq only in EL3 ...

We only can (and should only need to) configure cntfrq when running in
EL3 and executing this code in any other exception level will result
in exception.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>